49 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;  in si_dma_ring_get_wptr()
57 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;  in si_dma_ring_set_wptr()
120 	for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_stop()
135 	for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_start()
136 		ring = &adev->sdma.instance[i].ring;  in si_dma_start()
469 	adev->sdma.num_instances = 2;  in si_dma_early_init()
487 			      &adev->sdma.trap_irq);  in si_dma_sw_init()
493 			      &adev->sdma.trap_irq);  in si_dma_sw_init()
497 	for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_sw_init()
498 		ring = &adev->sdma.instance[i].ring;  in si_dma_sw_init()
503 				     &adev->sdma.trap_irq,  in si_dma_sw_init()
519 	for (i = 0; i < adev->sdma.num_instances; i++)  in si_dma_sw_fini()
520 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in si_dma_sw_fini()
636 		amdgpu_fence_process(&adev->sdma.instance[0].ring);  in si_dma_process_trap_irq()
638 		amdgpu_fence_process(&adev->sdma.instance[1].ring);  in si_dma_process_trap_irq()
653 		for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_set_clockgating_state()
665 		for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_set_clockgating_state()
747 	for (i = 0; i < adev->sdma.num_instances; i++)  in si_dma_set_ring_funcs()
748 		adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs;  in si_dma_set_ring_funcs()
758 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;  in si_dma_set_irq_funcs()
759 	adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs;  in si_dma_set_irq_funcs()
825 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in si_dma_set_buffer_funcs()
841 	for (i = 0; i < adev->sdma.num_instances; i++) {  in si_dma_set_vm_pte_funcs()
843 			&adev->sdma.instance[i].ring.sched;  in si_dma_set_vm_pte_funcs()
845 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in si_dma_set_vm_pte_funcs()