sdma_v6_0.c - OpenGrok cross reference for /Linux-v6.6/drivers/gpu/drm/amd/amdgpu/sdma_v6

Lines Matching refs:GC
214 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,  in sdma_v6_0_ring_set_wptr()
217 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,  in sdma_v6_0_ring_set_wptr()
387 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));  in sdma_v6_0_gfx_stop()
389 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_stop()
390 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));  in sdma_v6_0_gfx_stop()
392 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);  in sdma_v6_0_gfx_stop()
453 		f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_enable()
455 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);  in sdma_v6_0_enable()
482 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);  in sdma_v6_0_gfx_resume()
486 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));  in sdma_v6_0_gfx_resume()
494 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_resume()
497 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);  in sdma_v6_0_gfx_resume()
498 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);  in sdma_v6_0_gfx_resume()
499 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);  in sdma_v6_0_gfx_resume()
500 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);  in sdma_v6_0_gfx_resume()
504 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),  in sdma_v6_0_gfx_resume()
506 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),  in sdma_v6_0_gfx_resume()
510 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),  in sdma_v6_0_gfx_resume()
512 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),  in sdma_v6_0_gfx_resume()
519 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> …  in sdma_v6_0_gfx_resume()
520 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr …  in sdma_v6_0_gfx_resume()
525 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);  in sdma_v6_0_gfx_resume()
528 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring…  in sdma_v6_0_gfx_resume()
529 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(r…  in sdma_v6_0_gfx_resume()
532 		doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));  in sdma_v6_0_gfx_resume()
533 …doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_O…  in sdma_v6_0_gfx_resume()
542 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);  in sdma_v6_0_gfx_resume()
543 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_o…  in sdma_v6_0_gfx_resume()
554 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);  in sdma_v6_0_gfx_resume()
557 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));  in sdma_v6_0_gfx_resume()
560 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);  in sdma_v6_0_gfx_resume()
563 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));  in sdma_v6_0_gfx_resume()
569 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);  in sdma_v6_0_gfx_resume()
573 			temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_gfx_resume()
576 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);  in sdma_v6_0_gfx_resume()
581 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_resume()
583 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));  in sdma_v6_0_gfx_resume()
589 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);  in sdma_v6_0_gfx_resume()
729 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));  in sdma_v6_0_soft_reset()
731 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);  in sdma_v6_0_soft_reset()
732 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_soft_reset()
735 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);  in sdma_v6_0_soft_reset()
737 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);  in sdma_v6_0_soft_reset()
742 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);  in sdma_v6_0_soft_reset()
743 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in sdma_v6_0_soft_reset()
747 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);  in sdma_v6_0_soft_reset()
748 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in sdma_v6_0_soft_reset()
840 	m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,  in sdma_v6_0_mqd_init()