Lines Matching refs:adev
211 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) in nv_query_video_codecs()
217 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs()
221 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
222 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
234 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_query_video_codecs()
279 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
287 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
290 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
294 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
301 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
307 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
309 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
312 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
314 return adev->clock.spll.reference_freq; in nv_get_xclk()
318 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
330 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
358 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
363 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
370 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in nv_read_indexed_register()
371 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
375 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
383 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
388 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
397 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
403 *value = nv_get_register_value(adev, in nv_read_register()
411 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
416 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
419 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
421 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
423 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
425 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
427 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
430 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
431 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
438 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
444 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
453 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
456 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
469 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
476 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
480 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
482 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
483 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
486 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
487 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
490 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
491 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
494 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
495 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
502 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
508 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
514 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
516 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) in nv_program_aspm()
519 if (!(adev->flags & AMD_IS_APU) && in nv_program_aspm()
520 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
521 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
533 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
535 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
538 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
543 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
547 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
560 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
562 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
563 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
564 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
565 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
566 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
567 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
568 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
569 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
570 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
571 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
572 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
573 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
574 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
575 adev->doorbell_index.gfx_userqueue_start = in nv_init_doorbell_index()
577 adev->doorbell_index.gfx_userqueue_end = in nv_init_doorbell_index()
579 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in nv_init_doorbell_index()
580 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in nv_init_doorbell_index()
581 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
582 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
583 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
584 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
585 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
586 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
587 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
588 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
589 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
590 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
591 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
593 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
594 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
597 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
601 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
605 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in nv_update_umd_stable_pstate()
607 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in nv_update_umd_stable_pstate()
609 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
610 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
612 if (!(adev->flags & AMD_IS_APU) && in nv_update_umd_stable_pstate()
613 (adev->nbio.funcs->enable_aspm) && in nv_update_umd_stable_pstate()
614 amdgpu_device_should_use_aspm(adev)) in nv_update_umd_stable_pstate()
615 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
643 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
645 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
646 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
647 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
649 adev->smc_rreg = NULL; in nv_common_early_init()
650 adev->smc_wreg = NULL; in nv_common_early_init()
651 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in nv_common_early_init()
652 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in nv_common_early_init()
653 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in nv_common_early_init()
654 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in nv_common_early_init()
655 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in nv_common_early_init()
656 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in nv_common_early_init()
659 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
660 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
662 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
663 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
665 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
667 adev->rev_id = amdgpu_device_get_rev_id(adev); in nv_common_early_init()
668 adev->external_rev_id = 0xff; in nv_common_early_init()
672 switch (adev->ip_versions[GC_HWIP][0]) { in nv_common_early_init()
674 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
689 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
693 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
696 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
711 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
714 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
717 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
733 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
741 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
742 adev->rev_id = 0; in nv_common_early_init()
743 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
746 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
757 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
762 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
764 adev->cg_flags = 0; in nv_common_early_init()
765 adev->pg_flags = 0; in nv_common_early_init()
767 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
770 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
781 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
786 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
789 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
804 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
808 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
809 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
812 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
823 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
828 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
831 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
841 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
845 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
848 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
868 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
872 if (adev->pdev->device == 0x1681) in nv_common_early_init()
873 adev->external_rev_id = 0x20; in nv_common_early_init()
875 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
879 adev->cg_flags = 0; in nv_common_early_init()
880 adev->pg_flags = 0; in nv_common_early_init()
881 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
884 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
903 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
907 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
910 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
930 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
934 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
941 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
942 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
946 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
947 amdgpu_virt_init_setting(adev); in nv_common_early_init()
948 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
958 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
959 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
960 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { in nv_common_late_init()
961 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
967 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
978 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in nv_common_late_init()
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
987 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
988 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
1002 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1003 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1005 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
1006 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
1009 nv_program_aspm(adev); in nv_common_hw_init()
1011 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1016 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1017 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1019 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
1033 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1034 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in nv_common_hw_fini()
1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
1043 return nv_common_hw_fini(adev); in nv_common_suspend()
1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
1050 return nv_common_hw_init(adev); in nv_common_resume()
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1073 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1076 switch (adev->ip_versions[NBIO_HWIP][0]) { in nv_common_set_clockgating_state()
1084 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1086 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1088 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1090 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1110 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1113 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1115 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1117 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()