Lines Matching refs:mes
89 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, in mes_v10_1_submit_pkt_and_poll_completion() argument
97 struct amdgpu_device *adev = mes->adev; in mes_v10_1_submit_pkt_and_poll_completion()
98 struct amdgpu_ring *ring = &mes->ring; in mes_v10_1_submit_pkt_and_poll_completion()
103 spin_lock_irqsave(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
105 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; in mes_v10_1_submit_pkt_and_poll_completion()
111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; in mes_v10_1_submit_pkt_and_poll_completion()
115 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
147 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_add_hw_queue() argument
150 struct amdgpu_device *adev = mes->adev; in mes_v10_1_add_hw_queue()
184 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_add_hw_queue()
189 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_remove_hw_queue() argument
203 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_remove_hw_queue()
208 static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes, in mes_v10_1_unmap_legacy_queue() argument
237 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_unmap_legacy_queue()
242 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes, in mes_v10_1_suspend_gang() argument
248 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes, in mes_v10_1_resume_gang() argument
254 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) in mes_v10_1_query_sched_status() argument
264 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_query_sched_status()
269 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) in mes_v10_1_set_hw_resources() argument
272 struct amdgpu_device *adev = mes->adev; in mes_v10_1_set_hw_resources()
281 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v10_1_set_hw_resources()
282 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v10_1_set_hw_resources()
285 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; in mes_v10_1_set_hw_resources()
287 mes->query_status_fence_gpu_addr; in mes_v10_1_set_hw_resources()
291 mes->compute_hqd_mask[i]; in mes_v10_1_set_hw_resources()
294 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; in mes_v10_1_set_hw_resources()
297 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; in mes_v10_1_set_hw_resources()
301 mes->aggregated_doorbells[i]; in mes_v10_1_set_hw_resources()
315 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_set_hw_resources()
320 static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes) in mes_v10_1_init_aggregated_doorbell() argument
322 struct amdgpu_device *adev = mes->adev; in mes_v10_1_init_aggregated_doorbell()
329 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << in mes_v10_1_init_aggregated_doorbell()
338 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << in mes_v10_1_init_aggregated_doorbell()
347 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << in mes_v10_1_init_aggregated_doorbell()
356 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << in mes_v10_1_init_aggregated_doorbell()
365 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << in mes_v10_1_init_aggregated_doorbell()
391 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_buffer()
393 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_buffer()
399 &adev->mes.ucode_fw_obj[pipe], in mes_v10_1_allocate_ucode_buffer()
400 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_buffer()
401 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_buffer()
407 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_buffer()
409 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
410 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
424 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_data_buffer()
426 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_data_buffer()
432 &adev->mes.data_fw_obj[pipe], in mes_v10_1_allocate_ucode_data_buffer()
433 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_data_buffer()
434 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
440 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_data_buffer()
442 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
443 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
451 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
452 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
453 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
455 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
456 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
457 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
479 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_enable()
519 if (!adev->mes.fw[pipe]) in mes_v10_1_load_microcode()
540 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_load_microcode()
544 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
546 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
553 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
555 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
613 &adev->mes.eop_gpu_obj[pipe], in mes_v10_1_allocate_eop_buf()
614 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_allocate_eop_buf()
621 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size); in mes_v10_1_allocate_eop_buf()
623 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
624 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
816 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
825 r = mes_v10_1_mqd_init(&adev->mes.ring); in mes_v10_1_queue_init()
840 ring = &adev->mes.ring; in mes_v10_1_ring_init()
851 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; in mes_v10_1_ring_init()
875 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; in mes_v10_1_kiq_ring_init()
893 ring = &adev->mes.ring; in mes_v10_1_mqd_sw_init()
911 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); in mes_v10_1_mqd_sw_init()
912 if (!adev->mes.mqd_backup[pipe]) { in mes_v10_1_mqd_sw_init()
927 adev->mes.funcs = &mes_v10_1_funcs; in mes_v10_1_sw_init()
928 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; in mes_v10_1_sw_init()
965 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); in mes_v10_1_sw_fini()
966 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); in mes_v10_1_sw_fini()
969 kfree(adev->mes.mqd_backup[pipe]); in mes_v10_1_sw_fini()
971 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], in mes_v10_1_sw_fini()
972 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_sw_fini()
974 amdgpu_ucode_release(&adev->mes.fw[pipe]); in mes_v10_1_sw_fini()
981 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, in mes_v10_1_sw_fini()
982 &adev->mes.ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
983 &adev->mes.ring.mqd_ptr); in mes_v10_1_sw_fini()
986 amdgpu_ring_fini(&adev->mes.ring); in mes_v10_1_sw_fini()
1076 r = mes_v10_1_set_hw_resources(&adev->mes); in mes_v10_1_hw_init()
1080 mes_v10_1_init_aggregated_doorbell(&adev->mes); in mes_v10_1_hw_init()
1082 r = mes_v10_1_query_sched_status(&adev->mes); in mes_v10_1_hw_init()
1094 adev->mes.ring.sched.ready = true; in mes_v10_1_hw_init()
1107 adev->mes.ring.sched.ready = false; in mes_v10_1_hw_fini()