325 	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1);  in mes_v10_1_init_aggregated_doorbell()
332 	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1, data);  in mes_v10_1_init_aggregated_doorbell()
334 	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2);  in mes_v10_1_init_aggregated_doorbell()
341 	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2, data);  in mes_v10_1_init_aggregated_doorbell()
343 	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3);  in mes_v10_1_init_aggregated_doorbell()
350 	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3, data);  in mes_v10_1_init_aggregated_doorbell()
352 	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4);  in mes_v10_1_init_aggregated_doorbell()
359 	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4, data);  in mes_v10_1_init_aggregated_doorbell()
361 	data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5);  in mes_v10_1_init_aggregated_doorbell()
368 	WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5, data);  in mes_v10_1_init_aggregated_doorbell()
371 	WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data);  in mes_v10_1_init_aggregated_doorbell()
465 		data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);  in mes_v10_1_enable()
469 		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);  in mes_v10_1_enable()
478 			WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,  in mes_v10_1_enable()
485 		data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL);  in mes_v10_1_enable()
488 		WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data);  in mes_v10_1_enable()
494 		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);  in mes_v10_1_enable()
497 		data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);  in mes_v10_1_enable()
506 		WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);  in mes_v10_1_enable()
532 	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0);  in mes_v10_1_load_microcode()
539 	WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,  in mes_v10_1_load_microcode()
543 	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO,  in mes_v10_1_load_microcode()
545 	WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI,  in mes_v10_1_load_microcode()
549 	WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF);  in mes_v10_1_load_microcode()
552 	WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO,  in mes_v10_1_load_microcode()
554 	WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI,  in mes_v10_1_load_microcode()
558 	WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);  in mes_v10_1_load_microcode()
563 		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);  in mes_v10_1_load_microcode()
566 		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);  in mes_v10_1_load_microcode()
573 		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);  in mes_v10_1_load_microcode()
576 		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);  in mes_v10_1_load_microcode()
583 		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid);  in mes_v10_1_load_microcode()
586 		data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);  in mes_v10_1_load_microcode()
592 		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data);  in mes_v10_1_load_microcode()
595 		WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);  in mes_v10_1_load_microcode()
748 	data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID);
750 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data);
753 	data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
756 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
759 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
760 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
763 	data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
765 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0);
768 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
769 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
772 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
774 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
778 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
781 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
783 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
787 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
791 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
794 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
1003 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);  in mes_v10_1_kiq_setting()
1006 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);  in mes_v10_1_kiq_setting()
1008 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);  in mes_v10_1_kiq_setting()
1011 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);  in mes_v10_1_kiq_setting()
1014 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);  in mes_v10_1_kiq_setting()
1016 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);  in mes_v10_1_kiq_setting()