155 	adev->gmc.vm_fault.num_types = 1;  in gmc_v11_0_set_irq_funcs()
156 	adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;  in gmc_v11_0_set_irq_funcs()
159 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v11_0_set_irq_funcs()
160 		adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;  in gmc_v11_0_set_irq_funcs()
209 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v11_0_flush_vm_hub()
267 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v11_0_flush_vm_hub()
502 			adev->gmc.vram_start;  in gmc_v11_0_get_vm_pde()
505 	if (!adev->gmc.translate_further)  in gmc_v11_0_get_vm_pde()
585 	adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;  in gmc_v11_0_set_gmc_funcs()
648 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v11_0_early_init()
649 	adev->gmc.shared_aperture_end =  in gmc_v11_0_early_init()
650 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v11_0_early_init()
651 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v11_0_early_init()
652 	adev->gmc.private_aperture_end =  in gmc_v11_0_early_init()
653 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v11_0_early_init()
654 	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;  in gmc_v11_0_early_init()
672 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v11_0_late_init()
682 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v11_0_vram_gtt_location()
707 	adev->gmc.mc_vram_size =  in gmc_v11_0_mc_init()
709 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v11_0_mc_init()
716 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v11_0_mc_init()
717 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v11_0_mc_init()
721 		adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);  in gmc_v11_0_mc_init()
722 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v11_0_mc_init()
726 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v11_0_mc_init()
727 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)  in gmc_v11_0_mc_init()
728 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;  in gmc_v11_0_mc_init()
732 		adev->gmc.gart_size = 512ULL << 20;  in gmc_v11_0_mc_init()
734 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v11_0_mc_init()
736 	gmc_v11_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v11_0_mc_init()
769 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v11_0_sw_init()
773 	adev->gmc.vram_width = vram_width;  in gmc_v11_0_sw_init()
775 	adev->gmc.vram_type = vram_type;  in gmc_v11_0_sw_init()
776 	adev->gmc.vram_vendor = vram_vendor;  in gmc_v11_0_sw_init()
800 			      &adev->gmc.vm_fault);  in gmc_v11_0_sw_init()
807 			      &adev->gmc.vm_fault);  in gmc_v11_0_sw_init()
814 				      &adev->gmc.ecc_irq);  in gmc_v11_0_sw_init()
823 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v11_0_sw_init()
930 		 (unsigned int)(adev->gmc.gart_size >> 20),  in gmc_v11_0_gart_enable()
976 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v11_0_hw_fini()