190 	adev->gmc.vm_fault.num_types = 1;  in gmc_v10_0_set_irq_funcs()
191 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;  in gmc_v10_0_set_irq_funcs()
194 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v10_0_set_irq_funcs()
195 		adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;  in gmc_v10_0_set_irq_funcs()
248 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
306 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
597 	if (!adev->gmc.translate_further)  in gmc_v10_0_get_vm_pde()
677 	if (adev->gmc.gmc_funcs == NULL)  in gmc_v10_0_set_gmc_funcs()
678 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;  in gmc_v10_0_set_gmc_funcs()
742 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v10_0_early_init()
743 	adev->gmc.shared_aperture_end =  in gmc_v10_0_early_init()
744 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
745 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v10_0_early_init()
746 	adev->gmc.private_aperture_end =  in gmc_v10_0_early_init()
747 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
748 	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;  in gmc_v10_0_early_init()
766 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_late_init()
777 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
779 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v10_0_vram_gtt_location()
788 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
805 	adev->gmc.mc_vram_size =  in gmc_v10_0_mc_init()
807 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v10_0_mc_init()
814 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v10_0_mc_init()
815 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v10_0_mc_init()
819 		adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_mc_init()
820 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
824 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v10_0_mc_init()
830 			adev->gmc.gart_size = 512ULL << 20;  in gmc_v10_0_mc_init()
836 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v10_0_mc_init()
840 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v10_0_mc_init()
843 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v10_0_mc_init()
878 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v10_0_sw_init()
881 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;  in gmc_v10_0_sw_init()
882 		adev->gmc.vram_width = 64;  in gmc_v10_0_sw_init()
884 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;  in gmc_v10_0_sw_init()
885 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */  in gmc_v10_0_sw_init()
889 		adev->gmc.vram_width = vram_width;  in gmc_v10_0_sw_init()
891 		adev->gmc.vram_type = vram_type;  in gmc_v10_0_sw_init()
892 		adev->gmc.vram_vendor = vram_vendor;  in gmc_v10_0_sw_init()
897 		adev->gmc.mall_size = 128 * 1024 * 1024;  in gmc_v10_0_sw_init()
900 		adev->gmc.mall_size = 96 * 1024 * 1024;  in gmc_v10_0_sw_init()
903 		adev->gmc.mall_size = 32 * 1024 * 1024;  in gmc_v10_0_sw_init()
906 		adev->gmc.mall_size = 16 * 1024 * 1024;  in gmc_v10_0_sw_init()
909 		adev->gmc.mall_size = 0;  in gmc_v10_0_sw_init()
943 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
950 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
957 				      &adev->gmc.ecc_irq);  in gmc_v10_0_sw_init()
966 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v10_0_sw_init()
1079 		 (unsigned int)(adev->gmc.gart_size >> 20),  in gmc_v10_0_gart_enable()
1142 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_hw_fini()