56 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,  in gmc_v10_0_ecc_interrupt_state()  argument
65 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,  in gmc_v10_0_vm_fault_interrupt_state()  argument
72 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);  in gmc_v10_0_vm_fault_interrupt_state()
79 		if (!adev->in_s0ix)  in gmc_v10_0_vm_fault_interrupt_state()
80 			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);  in gmc_v10_0_vm_fault_interrupt_state()
84 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);  in gmc_v10_0_vm_fault_interrupt_state()
91 		if (!adev->in_s0ix)  in gmc_v10_0_vm_fault_interrupt_state()
92 			amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);  in gmc_v10_0_vm_fault_interrupt_state()
101 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,  in gmc_v10_0_process_interrupt()  argument
107 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];  in gmc_v10_0_process_interrupt()
121 		if (entry->ih != &adev->irq.ih_soft &&  in gmc_v10_0_process_interrupt()
122 		    amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,  in gmc_v10_0_process_interrupt()
129 		if (entry->ih == &adev->irq.ih) {  in gmc_v10_0_process_interrupt()
130 			amdgpu_irq_delegate(adev, entry, 8);  in gmc_v10_0_process_interrupt()
137 		if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault))  in gmc_v10_0_process_interrupt()
141 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_process_interrupt()
148 		    (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))  in gmc_v10_0_process_interrupt()
159 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);  in gmc_v10_0_process_interrupt()
161 	dev_err(adev->dev,  in gmc_v10_0_process_interrupt()
167 	dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",  in gmc_v10_0_process_interrupt()
171 	if (!amdgpu_sriov_vf(adev))  in gmc_v10_0_process_interrupt()
172 		hub->vmhub_funcs->print_l2_protection_fault_status(adev,  in gmc_v10_0_process_interrupt()
188 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_irq_funcs()  argument
190 	adev->gmc.vm_fault.num_types = 1;  in gmc_v10_0_set_irq_funcs()
191 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;  in gmc_v10_0_set_irq_funcs()
193 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_set_irq_funcs()
194 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v10_0_set_irq_funcs()
195 		adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;  in gmc_v10_0_set_irq_funcs()
206 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,  in gmc_v10_0_use_invalidate_semaphore()  argument
210 		(!amdgpu_sriov_vf(adev)));  in gmc_v10_0_use_invalidate_semaphore()
214 					struct amdgpu_device *adev,  in gmc_v10_0_get_atc_vmid_pasid_mapping_info()  argument
233 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_vm_hub()  argument
236 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);  in gmc_v10_0_flush_vm_hub()
237 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];  in gmc_v10_0_flush_vm_hub()
248 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
258 		for (i = 0; i < adev->usec_timeout; i++) {  in gmc_v10_0_flush_vm_hub()
268 		if (i >= adev->usec_timeout)  in gmc_v10_0_flush_vm_hub()
281 	    (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))  in gmc_v10_0_flush_vm_hub()
286 	for (i = 0; i < adev->usec_timeout; i++) {  in gmc_v10_0_flush_vm_hub()
306 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
308 	if (i < adev->usec_timeout)  in gmc_v10_0_flush_vm_hub()
324 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_gpu_tlb()  argument
327 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;  in gmc_v10_0_flush_gpu_tlb()
334 	adev->hdp.funcs->flush_hdp(adev, NULL);  in gmc_v10_0_flush_gpu_tlb()
339 	if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&  in gmc_v10_0_flush_gpu_tlb()
340 	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&  in gmc_v10_0_flush_gpu_tlb()
341 	    down_read_trylock(&adev->reset_domain->sem)) {  in gmc_v10_0_flush_gpu_tlb()
342 		struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];  in gmc_v10_0_flush_gpu_tlb()
348 		amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,  in gmc_v10_0_flush_gpu_tlb()
351 		up_read(&adev->reset_domain->sem);  in gmc_v10_0_flush_gpu_tlb()
355 	mutex_lock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
358 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB0(0), 0);  in gmc_v10_0_flush_gpu_tlb()
359 		mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
365 	if (!adev->mman.buffer_funcs_enabled ||  in gmc_v10_0_flush_gpu_tlb()
366 	    !adev->ib_pool_ready ||  in gmc_v10_0_flush_gpu_tlb()
367 	    amdgpu_in_reset(adev) ||  in gmc_v10_0_flush_gpu_tlb()
369 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB(0), 0);  in gmc_v10_0_flush_gpu_tlb()
370 		mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
379 	r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,  in gmc_v10_0_flush_gpu_tlb()
386 	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);  in gmc_v10_0_flush_gpu_tlb()
392 	mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
400 	mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
415 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,  in gmc_v10_0_flush_gpu_tlb_pasid()  argument
424 	u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;  in gmc_v10_0_flush_gpu_tlb_pasid()
425 	struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;  in gmc_v10_0_flush_gpu_tlb_pasid()
426 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in gmc_v10_0_flush_gpu_tlb_pasid()
429 		spin_lock(&adev->gfx.kiq[0].ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
437 			spin_unlock(&adev->gfx.kiq[0].ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
442 		spin_unlock(&adev->gfx.kiq[0].ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
445 			dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);  in gmc_v10_0_flush_gpu_tlb_pasid()
454 		ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
458 				for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)  in gmc_v10_0_flush_gpu_tlb_pasid()
459 					gmc_v10_0_flush_gpu_tlb(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
462 				gmc_v10_0_flush_gpu_tlb(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
465 			if (!adev->enable_mes)  in gmc_v10_0_flush_gpu_tlb_pasid()
476 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);  in gmc_v10_0_emit_flush_gpu_tlb()
477 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];  in gmc_v10_0_emit_flush_gpu_tlb()
524 	struct amdgpu_device *adev = ring->adev;  in gmc_v10_0_emit_pasid_mapping()  local
572 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)  in gmc_v10_0_map_mtype()  argument
590 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,  in gmc_v10_0_get_vm_pde()  argument
594 		*addr = amdgpu_gmc_vram_mc2pa(adev, *addr);  in gmc_v10_0_get_vm_pde()
597 	if (!adev->gmc.translate_further)  in gmc_v10_0_get_vm_pde()
613 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,  in gmc_v10_0_get_vm_pte()  argument
642 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)  in gmc_v10_0_get_vbios_fb_size()  argument
675 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_gmc_funcs()  argument
677 	if (adev->gmc.gmc_funcs == NULL)  in gmc_v10_0_set_gmc_funcs()
678 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;  in gmc_v10_0_set_gmc_funcs()
681 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_umc_funcs()  argument
683 	switch (adev->ip_versions[UMC_HWIP][0]) {  in gmc_v10_0_set_umc_funcs()
685 		adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;  in gmc_v10_0_set_umc_funcs()
686 		adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
687 		adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
688 		adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;  in gmc_v10_0_set_umc_funcs()
689 		adev->umc.retire_unit = 1;  in gmc_v10_0_set_umc_funcs()
690 		adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];  in gmc_v10_0_set_umc_funcs()
691 		adev->umc.ras = &umc_v8_7_ras;  in gmc_v10_0_set_umc_funcs()
698 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_mmhub_funcs()  argument
700 	switch (adev->ip_versions[MMHUB_HWIP][0]) {  in gmc_v10_0_set_mmhub_funcs()
704 		adev->mmhub.funcs = &mmhub_v2_3_funcs;  in gmc_v10_0_set_mmhub_funcs()
707 		adev->mmhub.funcs = &mmhub_v2_0_funcs;  in gmc_v10_0_set_mmhub_funcs()
712 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_gfxhub_funcs()  argument
714 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_set_gfxhub_funcs()
723 		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;  in gmc_v10_0_set_gfxhub_funcs()
726 		adev->gfxhub.funcs = &gfxhub_v2_0_funcs;  in gmc_v10_0_set_gfxhub_funcs()
734 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_early_init()  local
736 	gmc_v10_0_set_mmhub_funcs(adev);  in gmc_v10_0_early_init()
737 	gmc_v10_0_set_gfxhub_funcs(adev);  in gmc_v10_0_early_init()
738 	gmc_v10_0_set_gmc_funcs(adev);  in gmc_v10_0_early_init()
739 	gmc_v10_0_set_irq_funcs(adev);  in gmc_v10_0_early_init()
740 	gmc_v10_0_set_umc_funcs(adev);  in gmc_v10_0_early_init()
742 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v10_0_early_init()
743 	adev->gmc.shared_aperture_end =  in gmc_v10_0_early_init()
744 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
745 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v10_0_early_init()
746 	adev->gmc.private_aperture_end =  in gmc_v10_0_early_init()
747 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
748 	adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;  in gmc_v10_0_early_init()
755 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_late_init()  local
758 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);  in gmc_v10_0_late_init()
762 	r = amdgpu_gmc_ras_late_init(adev);  in gmc_v10_0_late_init()
766 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_late_init()
769 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,  in gmc_v10_0_vram_gtt_location()  argument
774 	base = adev->gfxhub.funcs->get_fb_location(adev);  in gmc_v10_0_vram_gtt_location()
777 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
779 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v10_0_vram_gtt_location()
780 	amdgpu_gmc_gart_location(adev, mc);  in gmc_v10_0_vram_gtt_location()
781 	amdgpu_gmc_agp_location(adev, mc);  in gmc_v10_0_vram_gtt_location()
784 	adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_vram_gtt_location()
787 	adev->vm_manager.vram_base_offset +=  in gmc_v10_0_vram_gtt_location()
788 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
800 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)  in gmc_v10_0_mc_init()  argument
805 	adev->gmc.mc_vram_size =  in gmc_v10_0_mc_init()
806 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;  in gmc_v10_0_mc_init()
807 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v10_0_mc_init()
809 	if (!(adev->flags & AMD_IS_APU)) {  in gmc_v10_0_mc_init()
810 		r = amdgpu_device_resize_fb_bar(adev);  in gmc_v10_0_mc_init()
814 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v10_0_mc_init()
815 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v10_0_mc_init()
818 	if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {  in gmc_v10_0_mc_init()
819 		adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_mc_init()
820 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
824 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v10_0_mc_init()
828 		switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_mc_init()
830 			adev->gmc.gart_size = 512ULL << 20;  in gmc_v10_0_mc_init()
836 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v10_0_mc_init()
840 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v10_0_mc_init()
843 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v10_0_mc_init()
848 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)  in gmc_v10_0_gart_init()  argument
852 	if (adev->gart.bo) {  in gmc_v10_0_gart_init()
858 	r = amdgpu_gart_init(adev);  in gmc_v10_0_gart_init()
862 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;  in gmc_v10_0_gart_init()
863 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |  in gmc_v10_0_gart_init()
866 	return amdgpu_gart_table_vram_alloc(adev);  in gmc_v10_0_gart_init()
872 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_sw_init()  local
874 	adev->gfxhub.funcs->init(adev);  in gmc_v10_0_sw_init()
876 	adev->mmhub.funcs->init(adev);  in gmc_v10_0_sw_init()
878 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v10_0_sw_init()
880 	if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {  in gmc_v10_0_sw_init()
881 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;  in gmc_v10_0_sw_init()
882 		adev->gmc.vram_width = 64;  in gmc_v10_0_sw_init()
884 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;  in gmc_v10_0_sw_init()
885 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */  in gmc_v10_0_sw_init()
887 		r = amdgpu_atomfirmware_get_vram_info(adev,  in gmc_v10_0_sw_init()
889 		adev->gmc.vram_width = vram_width;  in gmc_v10_0_sw_init()
891 		adev->gmc.vram_type = vram_type;  in gmc_v10_0_sw_init()
892 		adev->gmc.vram_vendor = vram_vendor;  in gmc_v10_0_sw_init()
895 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_sw_init()
897 		adev->gmc.mall_size = 128 * 1024 * 1024;  in gmc_v10_0_sw_init()
900 		adev->gmc.mall_size = 96 * 1024 * 1024;  in gmc_v10_0_sw_init()
903 		adev->gmc.mall_size = 32 * 1024 * 1024;  in gmc_v10_0_sw_init()
906 		adev->gmc.mall_size = 16 * 1024 * 1024;  in gmc_v10_0_sw_init()
909 		adev->gmc.mall_size = 0;  in gmc_v10_0_sw_init()
913 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_sw_init()
927 		set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);  in gmc_v10_0_sw_init()
928 		set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);  in gmc_v10_0_sw_init()
934 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);  in gmc_v10_0_sw_init()
941 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,  in gmc_v10_0_sw_init()
943 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
948 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,  in gmc_v10_0_sw_init()
950 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
954 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_sw_init()
956 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,  in gmc_v10_0_sw_init()
957 				      &adev->gmc.ecc_irq);  in gmc_v10_0_sw_init()
966 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v10_0_sw_init()
968 	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));  in gmc_v10_0_sw_init()
970 		dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");  in gmc_v10_0_sw_init()
974 	adev->need_swiotlb = drm_need_swiotlb(44);  in gmc_v10_0_sw_init()
976 	r = gmc_v10_0_mc_init(adev);  in gmc_v10_0_sw_init()
980 	amdgpu_gmc_get_vbios_allocations(adev);  in gmc_v10_0_sw_init()
983 	r = amdgpu_bo_init(adev);  in gmc_v10_0_sw_init()
987 	r = gmc_v10_0_gart_init(adev);  in gmc_v10_0_sw_init()
997 	adev->vm_manager.first_kfd_vmid = 8;  in gmc_v10_0_sw_init()
999 	amdgpu_vm_manager_init(adev);  in gmc_v10_0_sw_init()
1001 	r = amdgpu_gmc_ras_sw_init(adev);  in gmc_v10_0_sw_init()
1015 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)  in gmc_v10_0_gart_fini()  argument
1017 	amdgpu_gart_table_vram_free(adev);  in gmc_v10_0_gart_fini()
1022 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_sw_fini()  local
1024 	amdgpu_vm_manager_fini(adev);  in gmc_v10_0_sw_fini()
1025 	gmc_v10_0_gart_fini(adev);  in gmc_v10_0_sw_fini()
1026 	amdgpu_gem_force_release(adev);  in gmc_v10_0_sw_fini()
1027 	amdgpu_bo_fini(adev);  in gmc_v10_0_sw_fini()
1032 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)  in gmc_v10_0_init_golden_registers()  argument
1041 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)  in gmc_v10_0_gart_enable()  argument
1046 	if (adev->gart.bo == NULL) {  in gmc_v10_0_gart_enable()
1047 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");  in gmc_v10_0_gart_enable()
1051 	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);  in gmc_v10_0_gart_enable()
1053 	if (!adev->in_s0ix) {  in gmc_v10_0_gart_enable()
1054 		r = adev->gfxhub.funcs->gart_enable(adev);  in gmc_v10_0_gart_enable()
1059 	r = adev->mmhub.funcs->gart_enable(adev);  in gmc_v10_0_gart_enable()
1063 	adev->hdp.funcs->init_registers(adev);  in gmc_v10_0_gart_enable()
1066 	adev->hdp.funcs->flush_hdp(adev, NULL);  in gmc_v10_0_gart_enable()
1071 	if (!adev->in_s0ix)  in gmc_v10_0_gart_enable()
1072 		adev->gfxhub.funcs->set_fault_enable_default(adev, value);  in gmc_v10_0_gart_enable()
1073 	adev->mmhub.funcs->set_fault_enable_default(adev, value);  in gmc_v10_0_gart_enable()
1074 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);  in gmc_v10_0_gart_enable()
1075 	if (!adev->in_s0ix)  in gmc_v10_0_gart_enable()
1076 		gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);  in gmc_v10_0_gart_enable()
1079 		 (unsigned int)(adev->gmc.gart_size >> 20),  in gmc_v10_0_gart_enable()
1080 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));  in gmc_v10_0_gart_enable()
1088 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_hw_init()  local
1091 	gmc_v10_0_init_golden_registers(adev);  in gmc_v10_0_hw_init()
1097 	if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)  in gmc_v10_0_hw_init()
1098 		adev->gfxhub.funcs->utcl2_harvest(adev);  in gmc_v10_0_hw_init()
1100 	r = gmc_v10_0_gart_enable(adev);  in gmc_v10_0_hw_init()
1105 		r = amdgpu_gmc_vram_checking(adev);  in gmc_v10_0_hw_init()
1110 	if (adev->umc.funcs && adev->umc.funcs->init_registers)  in gmc_v10_0_hw_init()
1111 		adev->umc.funcs->init_registers(adev);  in gmc_v10_0_hw_init()
1123 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)  in gmc_v10_0_gart_disable()  argument
1125 	if (!adev->in_s0ix)  in gmc_v10_0_gart_disable()
1126 		adev->gfxhub.funcs->gart_disable(adev);  in gmc_v10_0_gart_disable()
1127 	adev->mmhub.funcs->gart_disable(adev);  in gmc_v10_0_gart_disable()
1132 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_hw_fini()  local
1134 	gmc_v10_0_gart_disable(adev);  in gmc_v10_0_hw_fini()
1136 	if (amdgpu_sriov_vf(adev)) {  in gmc_v10_0_hw_fini()
1142 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_hw_fini()
1149 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_suspend()  local
1151 	gmc_v10_0_hw_fini(adev);  in gmc_v10_0_suspend()
1159 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_resume()  local
1161 	r = gmc_v10_0_hw_init(adev);  in gmc_v10_0_resume()
1165 	amdgpu_vmid_reset_all(adev);  in gmc_v10_0_resume()
1191 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_set_clockgating_state()  local
1198 	if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {  in gmc_v10_0_set_clockgating_state()
1199 		dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");  in gmc_v10_0_set_clockgating_state()
1203 	r = adev->mmhub.funcs->set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1207 	if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))  in gmc_v10_0_set_clockgating_state()
1208 		return athub_v2_1_set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1210 		return athub_v2_0_set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1215 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_get_clockgating_state()  local
1217 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||  in gmc_v10_0_get_clockgating_state()
1218 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))  in gmc_v10_0_get_clockgating_state()
1221 	adev->mmhub.funcs->get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()
1223 	if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))  in gmc_v10_0_get_clockgating_state()
1224 		athub_v2_1_get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()
1226 		athub_v2_0_get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()