Lines Matching refs:GC
106 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); in gfxhub_v3_0_get_fb_location()
116 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; in gfxhub_v3_0_get_mc_fb_offset()
124 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v3_0_setup_vm_pt_regs()
128 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v3_0_setup_vm_pt_regs()
139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs()
141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs()
144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_init_gart_aperture_regs()
146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_init_gart_aperture_regs()
155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); in gfxhub_v3_0_init_system_aperture_regs()
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v3_0_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v3_0_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v3_0_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v3_0_init_system_aperture_regs()
169 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v3_0_init_system_aperture_regs()
171 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v3_0_init_system_aperture_regs()
175 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v3_0_init_system_aperture_regs()
177 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v3_0_init_system_aperture_regs()
180 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v3_0_init_system_aperture_regs()
190 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_init_tlb_regs()
216 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); in gfxhub_v3_0_init_cache_regs()
227 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); in gfxhub_v3_0_init_cache_regs()
229 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); in gfxhub_v3_0_init_cache_regs()
232 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); in gfxhub_v3_0_init_cache_regs()
244 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); in gfxhub_v3_0_init_cache_regs()
249 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); in gfxhub_v3_0_init_cache_regs()
253 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); in gfxhub_v3_0_init_cache_regs()
260 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_enable_system_domain()
265 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v3_0_enable_system_domain()
276 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v3_0_disable_identity_aperture()
278 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, in gfxhub_v3_0_disable_identity_aperture()
281 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, in gfxhub_v3_0_disable_identity_aperture()
283 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, in gfxhub_v3_0_disable_identity_aperture()
286 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); in gfxhub_v3_0_disable_identity_aperture()
287 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); in gfxhub_v3_0_disable_identity_aperture()
298 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); in gfxhub_v3_0_setup_vmid_config()
323 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, in gfxhub_v3_0_setup_vmid_config()
325 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v3_0_setup_vmid_config()
327 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v3_0_setup_vmid_config()
329 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v3_0_setup_vmid_config()
332 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v3_0_setup_vmid_config()
346 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, in gfxhub_v3_0_program_invalidation()
348 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, in gfxhub_v3_0_program_invalidation()
361 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE, in gfxhub_v3_0_gart_enable()
363 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP, in gfxhub_v3_0_gart_enable()
389 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, in gfxhub_v3_0_gart_disable()
393 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v3_0_gart_disable()
397 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v3_0_gart_disable()
400 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v3_0_gart_disable()
401 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); in gfxhub_v3_0_gart_disable()
416 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v3_0_set_fault_enable_default()
418 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v3_0_set_fault_enable_default()
426 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_set_fault_enable_default()
456 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v3_0_set_fault_enable_default()
469 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_init()
472 SOC15_REG_OFFSET(GC, 0, in gfxhub_v3_0_init()
475 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM); in gfxhub_v3_0_init()
477 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ); in gfxhub_v3_0_init()
479 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK); in gfxhub_v3_0_init()
481 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); in gfxhub_v3_0_init()
483 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v3_0_init()
485 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v3_0_init()