Lines Matching refs:GC
107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_0_get_fb_location()
117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_0_get_mc_fb_offset()
125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_setup_vm_pt_regs()
129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_setup_vm_pt_regs()
140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_0_init_system_aperture_regs()
162 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v2_0_init_system_aperture_regs()
171 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v2_0_init_system_aperture_regs()
176 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v2_0_init_system_aperture_regs()
178 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v2_0_init_system_aperture_regs()
181 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v2_0_init_system_aperture_regs()
191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
202 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
214 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_0_init_cache_regs()
225 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); in gfxhub_v2_0_init_cache_regs()
227 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_0_init_cache_regs()
230 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); in gfxhub_v2_0_init_cache_regs()
242 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); in gfxhub_v2_0_init_cache_regs()
247 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); in gfxhub_v2_0_init_cache_regs()
251 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); in gfxhub_v2_0_init_cache_regs()
258 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_enable_system_domain()
263 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); in gfxhub_v2_0_enable_system_domain()
268 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v2_0_disable_identity_aperture()
270 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, in gfxhub_v2_0_disable_identity_aperture()
273 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, in gfxhub_v2_0_disable_identity_aperture()
275 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, in gfxhub_v2_0_disable_identity_aperture()
278 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); in gfxhub_v2_0_disable_identity_aperture()
279 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); in gfxhub_v2_0_disable_identity_aperture()
290 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); in gfxhub_v2_0_setup_vmid_config()
315 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, in gfxhub_v2_0_setup_vmid_config()
317 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_setup_vmid_config()
319 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_setup_vmid_config()
321 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_setup_vmid_config()
324 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_setup_vmid_config()
338 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, in gfxhub_v2_0_program_invalidation()
340 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, in gfxhub_v2_0_program_invalidation()
369 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, in gfxhub_v2_0_gart_disable()
373 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_gart_disable()
377 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_gart_disable()
381 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
382 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); in gfxhub_v2_0_gart_disable()
397 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_set_fault_enable_default()
427 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v2_0_set_fault_enable_default()
440 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
443 SOC15_REG_OFFSET(GC, 0, in gfxhub_v2_0_init()
446 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); in gfxhub_v2_0_init()
448 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); in gfxhub_v2_0_init()
450 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); in gfxhub_v2_0_init()
452 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_0_init()
454 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); in gfxhub_v2_0_init()
456 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_0_init()