2039 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache()
2083 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache()
2158 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2239 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_pfp_cache_rs64()
2280 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2362 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_me_cache_rs64()
2398 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2404 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_config_mec_cache_rs64()
2763 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2844 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2981 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3063 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3486 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3492 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);  in gfx_v11_0_cp_compute_load_microcode_rs64()
3605 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3612 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);  in gfx_v11_0_gfx_mqd_init()
3788 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v11_0_compute_mqd_init()