Lines Matching refs:GC
88 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
92 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
316 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
641 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
671 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
672 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
673 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
674 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
675 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
676 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
677 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
753 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
756 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
763 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
769 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1278 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1279 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1281 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v11_0_rlc_backdoor_autoload_enable()
1547 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
1554 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1558 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1573 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1577 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1639 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
1640 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
1643 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1645 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
1653 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1654 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1655 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1656 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1671 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1672 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1673 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1674 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1686 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1687 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
1700 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
1708 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
1718 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
1724 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
1743 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_enable_gui_idle_interrupt()
1754 WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
1761 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v11_0_init_csb()
1763 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v11_0_init_csb()
1765 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
1772 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
1775 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
1780 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
1782 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
1791 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
1805 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
1815 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
1824 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v11_0_rlc_enable_srm()
1827 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v11_0_rlc_enable_srm()
1841 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v11_0_load_rlcg_microcode()
1845 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v11_0_load_rlcg_microcode()
1848 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
1864 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
1869 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
1873 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1879 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
1883 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
1887 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
1889 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v11_0_load_rlc_iram_dram_microcode()
1892 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v11_0_load_rlc_iram_dram_microcode()
1908 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
1913 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
1917 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1919 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v11_0_load_rlcp_rlcv_microcode()
1921 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
1927 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
1932 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
1936 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
1938 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); in gfx_v11_0_load_rlcp_rlcv_microcode()
1940 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
1991 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
1994 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
2017 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2019 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2023 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2038 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache()
2043 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache()
2046 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache()
2048 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2061 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2063 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2067 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2082 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2087 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2090 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache()
2092 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache()
2105 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2108 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2112 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2127 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2131 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2134 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2136 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache()
2152 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache_rs64()
2154 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache_rs64()
2157 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2161 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2169 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2182 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2184 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2187 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2202 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_pfp_cache_rs64()
2205 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_pfp_cache_rs64()
2212 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2219 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2228 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2230 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_config_pfp_cache_rs64()
2232 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_config_pfp_cache_rs64()
2238 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2241 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2244 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2246 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2249 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2274 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache_rs64()
2276 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
2279 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2283 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2291 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2304 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2306 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2310 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2325 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2328 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_me_cache_rs64()
2335 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2342 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2351 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2353 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_config_me_cache_rs64()
2355 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_config_me_cache_rs64()
2361 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2364 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2367 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2369 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2372 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2397 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2401 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2403 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2406 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2412 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); in gfx_v11_0_config_mec_cache_rs64()
2413 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2416 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
2419 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_mec_cache_rs64()
2422 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
2423 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2430 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2432 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2436 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2449 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2451 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2455 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2487 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2490 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2496 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2499 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2504 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2509 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2512 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2518 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2521 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2526 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2531 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2534 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2540 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
2545 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2552 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2563 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v11_0_wait_for_rlc_autoload_complete()
2567 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
2570 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v11_0_wait_for_rlc_autoload_complete()
2633 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_enable()
2637 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
2640 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
2685 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2688 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, in gfx_v11_0_cp_gfx_load_pfp_microcode()
2691 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
2757 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2759 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2762 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2766 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2774 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2787 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2789 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2792 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2807 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2810 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2817 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2824 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2833 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2835 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2837 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2843 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2846 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2849 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2851 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2854 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2903 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_me_microcode()
2906 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, in gfx_v11_0_cp_gfx_load_me_microcode()
2909 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
2975 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2977 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2980 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2984 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
2992 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3005 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3007 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3011 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3026 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3029 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3036 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3043 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3052 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3054 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3056 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3062 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3065 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3068 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3070 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3073 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3127 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3129 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v11_0_cp_gfx_start()
3163 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
3199 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3202 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
3210 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_set_doorbell()
3220 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3224 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3226 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_gfx_set_doorbell()
3238 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v11_0_cp_gfx_resume()
3241 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
3252 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3256 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3257 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3261 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3262 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3266 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3268 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3272 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3275 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3276 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3278 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3292 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3295 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3296 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3299 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3300 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3303 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3305 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3309 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3312 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3313 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3314 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3335 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3356 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
3358 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3369 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
3415 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3418 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, in gfx_v11_0_cp_compute_load_microcode()
3421 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3485 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3489 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3491 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3494 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3500 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3501 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3504 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
3507 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3510 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3511 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3518 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3520 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3524 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3537 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3539 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3543 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3564 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3567 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3569 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3575 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3577 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3581 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3583 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3604 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v11_0_gfx_mqd_init()
3611 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); in gfx_v11_0_gfx_mqd_init()
3617 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); in gfx_v11_0_gfx_mqd_init()
3622 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); in gfx_v11_0_gfx_mqd_init()
3644 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); in gfx_v11_0_gfx_mqd_init()
3653 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_gfx_mqd_init()
3665 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
3751 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); in gfx_v11_0_compute_mqd_init()
3758 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
3787 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in gfx_v11_0_compute_mqd_init()
3797 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
3822 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
3837 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
3842 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); in gfx_v11_0_compute_mqd_init()
3847 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); in gfx_v11_0_compute_mqd_init()
3868 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
3871 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
3874 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
3876 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
3880 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
3884 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
3888 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
3889 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
3891 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
3895 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
3897 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
3899 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
3901 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
3906 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
3908 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
3912 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
3916 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
3918 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v11_0_kiq_init_register()
3922 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
3926 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
3928 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v11_0_kiq_init_register()
3932 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
3934 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
3939 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_kiq_init_register()
3941 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_kiq_init_register()
3945 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
3949 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
3951 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
3955 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
3957 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v11_0_kiq_init_register()
3961 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
3965 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
4192 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); in gfx_v11_0_select_cp_fw_arch()
4194 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4196 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); in gfx_v11_0_select_cp_fw_arch()
4198 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4209 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4245 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4247 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4249 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4251 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4400 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v11_0_is_idle()
4415 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v11_0_wait_for_idle()
4432 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4437 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4444 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_soft_reset()
4448 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_soft_reset()
4450 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
4451 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
4458 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_soft_reset()
4462 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_soft_reset()
4464 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); in gfx_v11_0_soft_reset()
4469 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
4473 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4474 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4475 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4478 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
4479 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) in gfx_v11_0_soft_reset()
4489 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4500 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4502 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4513 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4515 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); in gfx_v11_0_soft_reset()
4517 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); in gfx_v11_0_soft_reset()
4519 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); in gfx_v11_0_soft_reset()
4520 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
4523 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
4532 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4537 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4584 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
4585 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
4586 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
4588 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
4615 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
4620 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
4625 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
4630 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
4678 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
4690 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v11_0_set_safe_mode()
4694 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v11_0_set_safe_mode()
4703 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
4714 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_perf_clk()
4722 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_perf_clk()
4733 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_sram_fgcg()
4741 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_sram_fgcg()
4752 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_repeater_fgcg()
4760 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_repeater_fgcg()
4775 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
4782 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
4786 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
4793 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
4811 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_coarse_grain_clock_gating()
4824 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4827 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4842 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4845 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
4860 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4863 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
4870 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4872 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
4877 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4879 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4881 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4885 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4887 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4891 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4900 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4903 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
4911 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4913 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4915 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4919 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
4921 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
4960 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
4970 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
4972 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
4993 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5000 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
5007 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); in gfx_v11_cntl_power_gating()
5087 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_get_clockgating_state()
5104 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
5113 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
5137 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5138 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5181 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
5183 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
5454 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()
5703 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v11_0_ring_soft_recovery()
5716 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
5719 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
5732 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5737 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5740 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
5745 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
5767 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
5770 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
5773 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
5776 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
5789 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
5794 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5797 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
5802 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
5902 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
5921 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_inst_fault_state()
6004 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6010 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6013 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6015 tmp = RREG32_SOC15_IP(GC, target);
6018 WREG32_SOC15_IP(GC, target, tmp);
6020 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6023 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6025 tmp = RREG32_SOC15_IP(GC, target);
6028 WREG32_SOC15_IP(GC, target, tmp);
6297 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
6303 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
6304 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()