1246 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_afmt_audio_select_pin()
1249 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_audio_select_pin()
1250 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v11_0_afmt_audio_select_pin()
1251 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_audio_select_pin()
1267 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_latency_fields()
1297 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_latency_fields()
1314 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_speaker_allocation()
1338 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1351 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1384 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_sad_regs()
1437 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v11_0_audio_write_sad_regs()
1537 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1539 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1540 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1542 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1544 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1546 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1547 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1549 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1551 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1553 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1554 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1556 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1573 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1575 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1577 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1579 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1594 	if (!dig || !dig->afmt)  in dce_v11_0_audio_set_dto()
1627 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_setmode()
1631 	if (!dig->afmt->enabled)  in dce_v11_0_afmt_setmode()
1641 	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);  in dce_v11_0_afmt_setmode()
1642 	dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_setmode()
1646 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1648 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v11_0_afmt_setmode()
1650 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v11_0_afmt_setmode()
1652 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1677 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1679 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1683 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1685 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1690 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1692 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1695 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1697 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1700 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1702 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v11_0_afmt_setmode()
1704 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1709 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1711 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1714 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1716 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1725 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1729 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1731 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1733 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1735 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1737 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1744 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1748 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v11_0_afmt_setmode()
1769 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1774 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1776 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1778 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1780 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1783 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1785 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v11_0_afmt_setmode()
1786 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v11_0_afmt_setmode()
1787 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1788 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1791 	dce_v11_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v11_0_afmt_setmode()
1801 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_enable()
1805 	if (enable && dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1807 	if (!enable && !dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1810 	if (!enable && dig->afmt->pin) {  in dce_v11_0_afmt_enable()
1811 		dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_enable()
1812 		dig->afmt->pin = NULL;  in dce_v11_0_afmt_enable()
1815 	dig->afmt->enabled = enable;  in dce_v11_0_afmt_enable()
1818 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v11_0_afmt_enable()
1826 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_init()
1830 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v11_0_afmt_init()
1831 		if (adev->mode_info.afmt[i]) {  in dce_v11_0_afmt_init()
1832 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v11_0_afmt_init()
1833 			adev->mode_info.afmt[i]->id = i;  in dce_v11_0_afmt_init()
1837 				kfree(adev->mode_info.afmt[j]);  in dce_v11_0_afmt_init()
1838 				adev->mode_info.afmt[j] = NULL;  in dce_v11_0_afmt_init()
1851 		kfree(adev->mode_info.afmt[i]);  in dce_v11_0_afmt_fini()
1852 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_fini()
3501 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v11_0_encoder_prepare()