78 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in amdgpu_virt_kiq_reg_write_reg_wait()
552 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
553 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
554 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
555 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
556 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
557 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
558 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
559 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
560 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
844 		adev->gfx.is_poweron = false;  in amdgpu_virt_post_reset()
990 	if (!adev->gfx.rlc.rlcg_reg_access_supported) {  in amdgpu_virt_rlcg_reg_rw()
996 	if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {  in amdgpu_virt_rlcg_reg_rw()
1001 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id];  in amdgpu_virt_rlcg_reg_rw()