45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)  in amdgpu_virt_mmio_blocked()  argument
53 void amdgpu_virt_init_setting(struct amdgpu_device *adev)  in amdgpu_virt_init_setting()  argument
55 	struct drm_device *ddev = adev_to_drm(adev);  in amdgpu_virt_init_setting()
58 	if (adev->asic_type != CHIP_ALDEBARAN &&  in amdgpu_virt_init_setting()
59 	    adev->asic_type != CHIP_ARCTURUS &&  in amdgpu_virt_init_setting()
60 	    ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) {  in amdgpu_virt_init_setting()
61 		if (adev->mode_info.num_crtc == 0)  in amdgpu_virt_init_setting()
62 			adev->mode_info.num_crtc = 1;  in amdgpu_virt_init_setting()
63 		adev->enable_virtual_display = true;  in amdgpu_virt_init_setting()
66 	adev->cg_flags = 0;  in amdgpu_virt_init_setting()
67 	adev->pg_flags = 0;  in amdgpu_virt_init_setting()
74 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,  in amdgpu_virt_kiq_reg_write_reg_wait()  argument
78 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in amdgpu_virt_kiq_reg_write_reg_wait()
84 	if (adev->mes.ring.sched.ready) {  in amdgpu_virt_kiq_reg_write_reg_wait()
85 		amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,  in amdgpu_virt_kiq_reg_write_reg_wait()
123 	dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);  in amdgpu_virt_kiq_reg_write_reg_wait()
133 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_request_full_gpu()  argument
135 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_full_gpu()
139 		r = virt->ops->req_full_gpu(adev, init);  in amdgpu_virt_request_full_gpu()
143 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_request_full_gpu()
156 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_release_full_gpu()  argument
158 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_full_gpu()
162 		r = virt->ops->rel_full_gpu(adev, init);  in amdgpu_virt_release_full_gpu()
166 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_release_full_gpu()
177 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)  in amdgpu_virt_reset_gpu()  argument
179 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_reset_gpu()
183 		r = virt->ops->reset_gpu(adev);  in amdgpu_virt_reset_gpu()
187 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_reset_gpu()
193 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)  in amdgpu_virt_request_init_data()  argument
195 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_init_data()
198 		virt->ops->req_init_data(adev);  in amdgpu_virt_request_init_data()
200 	if (adev->virt.req_init_data_ver > 0)  in amdgpu_virt_request_init_data()
212 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)  in amdgpu_virt_wait_reset()  argument
214 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_wait_reset()
219 	return virt->ops->wait_reset(adev);  in amdgpu_virt_wait_reset()
228 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_alloc_mm_table()  argument
232 	if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)  in amdgpu_virt_alloc_mm_table()
235 	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,  in amdgpu_virt_alloc_mm_table()
238 				    &adev->virt.mm_table.bo,  in amdgpu_virt_alloc_mm_table()
239 				    &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
240 				    (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
246 	memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);  in amdgpu_virt_alloc_mm_table()
248 		 adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
249 		 adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
258 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_free_mm_table()  argument
260 	if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)  in amdgpu_virt_free_mm_table()
263 	amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,  in amdgpu_virt_free_mm_table()
264 			      &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_free_mm_table()
265 			      (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_free_mm_table()
266 	adev->virt.mm_table.gpu_addr = 0;  in amdgpu_virt_free_mm_table()
290 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_init_ras_err_handler_data()  argument
292 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_init_ras_err_handler_data()
330 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)  in amdgpu_virt_ras_release_bp()  argument
332 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_release_bp()
348 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_release_ras_err_handler_data()  argument
350 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_ras_err_handler_data()
358 	amdgpu_virt_ras_release_bp(adev);  in amdgpu_virt_release_ras_err_handler_data()
366 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,  in amdgpu_virt_ras_add_bps()  argument
369 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_add_bps()
379 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)  in amdgpu_virt_ras_reserve_bps()  argument
381 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_reserve_bps()
398 		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,  in amdgpu_virt_ras_reserve_bps()
409 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_ras_check_bad_page()  argument
412 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_check_bad_page()
426 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_add_bad_page()  argument
434 	if (adev->mman.fw_vram_usage_va)  in amdgpu_virt_add_bad_page()
435 		vram_usage_va = adev->mman.fw_vram_usage_va;  in amdgpu_virt_add_bad_page()
437 		vram_usage_va = adev->mman.drv_vram_usage_va;  in amdgpu_virt_add_bad_page()
446 			if (amdgpu_virt_ras_check_bad_page(adev, retired_page))  in amdgpu_virt_add_bad_page()
449 			amdgpu_virt_ras_add_bps(adev, &bp, 1);  in amdgpu_virt_add_bad_page()
451 			amdgpu_virt_ras_reserve_bps(adev);  in amdgpu_virt_add_bad_page()
456 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)  in amdgpu_virt_read_pf2vf_data()  argument
458 	struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_read_pf2vf_data()
465 	if (adev->virt.fw_reserve.p_pf2vf == NULL)  in amdgpu_virt_read_pf2vf_data()
477 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
478 			adev->virt.fw_reserve.checksum_key, checksum);  in amdgpu_virt_read_pf2vf_data()
484 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
491 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
498 		adev->virt.vf2pf_update_interval_ms =  in amdgpu_virt_read_pf2vf_data()
500 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
502 		adev->virt.reg_access =  in amdgpu_virt_read_pf2vf_data()
505 		adev->virt.decode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
506 		adev->virt.decode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
507 		adev->virt.encode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
508 		adev->virt.encode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
509 		adev->virt.is_mm_bw_enabled = false;  in amdgpu_virt_read_pf2vf_data()
512 			adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
515 			adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
518 			adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
521 			adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
523 		if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))  in amdgpu_virt_read_pf2vf_data()
524 			adev->virt.is_mm_bw_enabled = true;  in amdgpu_virt_read_pf2vf_data()
526 		adev->unique_id =  in amdgpu_virt_read_pf2vf_data()
535 	if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)  in amdgpu_virt_read_pf2vf_data()
536 		adev->virt.vf2pf_update_interval_ms = 2000;  in amdgpu_virt_read_pf2vf_data()
541 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)  in amdgpu_virt_populate_vf2pf_ucode_info()  argument
544 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_populate_vf2pf_ucode_info()
546 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_populate_vf2pf_ucode_info()
549 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
550 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
551 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
552 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
553 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
554 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
555 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
556 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
557 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
558 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
559 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
560 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
561 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
563 			    adev->psp.asd_context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
565 			    adev->psp.ras_context.context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
567 			    adev->psp.xgmi_context.context.bin_desc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
568 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
569 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
570 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
571 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
572 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
575 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)  in amdgpu_virt_write_vf2pf_data()  argument
579 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_write_vf2pf_data()
581 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_write_vf2pf_data()
601 		ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;  in amdgpu_virt_write_vf2pf_data()
603 		amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;  in amdgpu_virt_write_vf2pf_data()
604 	vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
605 	vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
607 	amdgpu_virt_populate_vf2pf_ucode_info(adev);  in amdgpu_virt_write_vf2pf_data()
615 	vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;  in amdgpu_virt_write_vf2pf_data()
625 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);  in amdgpu_virt_update_vf2pf_work_item()  local
628 	ret = amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
631 	amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
634 	schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);  in amdgpu_virt_update_vf2pf_work_item()
637 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_fini_data_exchange()  argument
639 	if (adev->virt.vf2pf_update_interval_ms != 0) {  in amdgpu_virt_fini_data_exchange()
641 		cancel_delayed_work_sync(&adev->virt.vf2pf_work);  in amdgpu_virt_fini_data_exchange()
642 		adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_fini_data_exchange()
646 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_init_data_exchange()  argument
648 	adev->virt.fw_reserve.p_pf2vf = NULL;  in amdgpu_virt_init_data_exchange()
649 	adev->virt.fw_reserve.p_vf2pf = NULL;  in amdgpu_virt_init_data_exchange()
650 	adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_init_data_exchange()
652 	if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) {  in amdgpu_virt_init_data_exchange()
654 	} else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {  in amdgpu_virt_init_data_exchange()
656 		amdgpu_virt_exchange_data(adev);  in amdgpu_virt_init_data_exchange()
658 		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);  in amdgpu_virt_init_data_exchange()
659 …schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_…  in amdgpu_virt_init_data_exchange()
660 	} else if (adev->bios != NULL) {  in amdgpu_virt_init_data_exchange()
662 		adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_init_data_exchange()
664 			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_init_data_exchange()
666 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_init_data_exchange()
671 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)  in amdgpu_virt_exchange_data()  argument
677 	if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {  in amdgpu_virt_exchange_data()
678 		if (adev->mman.fw_vram_usage_va) {  in amdgpu_virt_exchange_data()
679 			adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_exchange_data()
681 				(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
682 			adev->virt.fw_reserve.p_vf2pf =  in amdgpu_virt_exchange_data()
684 				(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
685 		} else if (adev->mman.drv_vram_usage_va) {  in amdgpu_virt_exchange_data()
686 			adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_exchange_data()
688 				(adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
689 			adev->virt.fw_reserve.p_vf2pf =  in amdgpu_virt_exchange_data()
691 				(adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));  in amdgpu_virt_exchange_data()
694 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_exchange_data()
695 		amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_exchange_data()
698 		if (adev->virt.fw_reserve.p_pf2vf->version == 2) {  in amdgpu_virt_exchange_data()
699 			pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_exchange_data()
705 			if (bp_block_size && !adev->virt.ras_init_done)  in amdgpu_virt_exchange_data()
706 				amdgpu_virt_init_ras_err_handler_data(adev);  in amdgpu_virt_exchange_data()
708 			if (adev->virt.ras_init_done)  in amdgpu_virt_exchange_data()
709 				amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);  in amdgpu_virt_exchange_data()
714 void amdgpu_detect_virtualization(struct amdgpu_device *adev)  in amdgpu_detect_virtualization()  argument
718 	switch (adev->asic_type) {  in amdgpu_detect_virtualization()
739 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;  in amdgpu_detect_virtualization()
742 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;  in amdgpu_detect_virtualization()
747 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in amdgpu_detect_virtualization()
750 	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)  in amdgpu_detect_virtualization()
754 		adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;  in amdgpu_detect_virtualization()
757 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_detect_virtualization()
758 		switch (adev->asic_type) {  in amdgpu_detect_virtualization()
761 			vi_set_virt_ops(adev);  in amdgpu_detect_virtualization()
764 			soc15_set_virt_ops(adev);  in amdgpu_detect_virtualization()
770 				amdgpu_virt_request_init_data(adev);  in amdgpu_detect_virtualization()
775 			soc15_set_virt_ops(adev);  in amdgpu_detect_virtualization()
781 			nv_set_virt_ops(adev);  in amdgpu_detect_virtualization()
783 			amdgpu_virt_request_init_data(adev);  in amdgpu_detect_virtualization()
786 			DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);  in amdgpu_detect_virtualization()
792 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_mmio()  argument
794 	return amdgpu_sriov_is_debug(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_mmio()
797 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_kiq()  argument
799 	return amdgpu_sriov_is_normal(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_kiq()
802 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_enable_access_debugfs()  argument
804 	if (!amdgpu_sriov_vf(adev) ||  in amdgpu_virt_enable_access_debugfs()
805 	    amdgpu_virt_access_debugfs_is_kiq(adev))  in amdgpu_virt_enable_access_debugfs()
808 	if (amdgpu_virt_access_debugfs_is_mmio(adev))  in amdgpu_virt_enable_access_debugfs()
809 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_enable_access_debugfs()
816 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_disable_access_debugfs()  argument
818 	if (amdgpu_sriov_vf(adev))  in amdgpu_virt_disable_access_debugfs()
819 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_disable_access_debugfs()
822 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)  in amdgpu_virt_get_sriov_vf_mode()  argument
826 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_virt_get_sriov_vf_mode()
827 		if (amdgpu_sriov_is_pp_one_vf(adev))  in amdgpu_virt_get_sriov_vf_mode()
838 void amdgpu_virt_post_reset(struct amdgpu_device *adev)  in amdgpu_virt_post_reset()  argument
840 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {  in amdgpu_virt_post_reset()
844 		adev->gfx.is_poweron = false;  in amdgpu_virt_post_reset()
848 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)  in amdgpu_virt_fw_load_skip_check()  argument
850 	switch (adev->ip_versions[MP0_HWIP][0]) {  in amdgpu_virt_fw_load_skip_check()
913 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,  in amdgpu_virt_update_sriov_video_codec()  argument
919 	if (!adev->virt.is_mm_bw_enabled)  in amdgpu_virt_update_sriov_video_codec()
924 			encode[i].max_width = adev->virt.encode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
925 			encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()
935 			decode[i].max_width = adev->virt.decode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
936 			decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()
945 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,  in amdgpu_virt_get_rlcg_reg_access_flag()  argument
953 		if (amdgpu_sriov_reg_indirect_gc(adev)) {  in amdgpu_virt_get_rlcg_reg_access_flag()
966 		if (amdgpu_sriov_reg_indirect_mmhub(adev) &&  in amdgpu_virt_get_rlcg_reg_access_flag()
978 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc…  in amdgpu_virt_rlcg_reg_rw()  argument
990 	if (!adev->gfx.rlc.rlcg_reg_access_supported) {  in amdgpu_virt_rlcg_reg_rw()
991 		dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
996 	if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {  in amdgpu_virt_rlcg_reg_rw()
997 		dev_err(adev->dev, "invalid xcc\n");  in amdgpu_virt_rlcg_reg_rw()
1001 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id];  in amdgpu_virt_rlcg_reg_rw()
1002 	scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;  in amdgpu_virt_rlcg_reg_rw()
1003 	scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;  in amdgpu_virt_rlcg_reg_rw()
1004 	scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;  in amdgpu_virt_rlcg_reg_rw()
1005 	scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;  in amdgpu_virt_rlcg_reg_rw()
1007 		spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;  in amdgpu_virt_rlcg_reg_rw()
1013 			writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));  in amdgpu_virt_rlcg_reg_rw()
1018 			writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));  in amdgpu_virt_rlcg_reg_rw()
1039 			if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {  in amdgpu_virt_rlcg_reg_rw()
1041 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1044 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1047 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1050 					dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1054 				dev_err(adev->dev,  in amdgpu_virt_rlcg_reg_rw()
1064 void amdgpu_sriov_wreg(struct amdgpu_device *adev,  in amdgpu_sriov_wreg()  argument
1070 	if (!amdgpu_sriov_runtime(adev) &&  in amdgpu_sriov_wreg()
1071 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {  in amdgpu_sriov_wreg()
1072 		amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id);  in amdgpu_sriov_wreg()
1082 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,  in amdgpu_sriov_rreg()  argument
1087 	if (!amdgpu_sriov_runtime(adev) &&  in amdgpu_sriov_rreg()
1088 		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))  in amdgpu_sriov_rreg()
1089 		return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id);  in amdgpu_sriov_rreg()