155 	if (adev->uvd.address_64_bit)  in amdgpu_uvd_create_msg_bo_helper()
192 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);  in amdgpu_uvd_sw_init()
263 	r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name);  in amdgpu_uvd_sw_init()
267 		amdgpu_ucode_release(&adev->uvd.fw);  in amdgpu_uvd_sw_init()
272 	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;  in amdgpu_uvd_sw_init()
274 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;  in amdgpu_uvd_sw_init()
293 			adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;  in amdgpu_uvd_sw_init()
295 		adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |  in amdgpu_uvd_sw_init()
300 		    (adev->uvd.fw_version < FW_1_66_16))  in amdgpu_uvd_sw_init()
312 		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;  in amdgpu_uvd_sw_init()
314 		adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);  in amdgpu_uvd_sw_init()
318 		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;  in amdgpu_uvd_sw_init()
322 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {  in amdgpu_uvd_sw_init()
323 		if (adev->uvd.harvest_config & (1 << j))  in amdgpu_uvd_sw_init()
328 					    &adev->uvd.inst[j].vcpu_bo,  in amdgpu_uvd_sw_init()
329 					    &adev->uvd.inst[j].gpu_addr,  in amdgpu_uvd_sw_init()
330 					    &adev->uvd.inst[j].cpu_addr);  in amdgpu_uvd_sw_init()
337 	for (i = 0; i < adev->uvd.max_handles; ++i) {  in amdgpu_uvd_sw_init()
338 		atomic_set(&adev->uvd.handles[i], 0);  in amdgpu_uvd_sw_init()
339 		adev->uvd.filp[i] = NULL;  in amdgpu_uvd_sw_init()
344 		adev->uvd.address_64_bit = true;  in amdgpu_uvd_sw_init()
346 	r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);  in amdgpu_uvd_sw_init()
352 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;  in amdgpu_uvd_sw_init()
355 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;  in amdgpu_uvd_sw_init()
358 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;  in amdgpu_uvd_sw_init()
361 		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;  in amdgpu_uvd_sw_init()
364 		adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;  in amdgpu_uvd_sw_init()
372 	void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);  in amdgpu_uvd_sw_fini()
375 	drm_sched_entity_destroy(&adev->uvd.entity);  in amdgpu_uvd_sw_fini()
377 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {  in amdgpu_uvd_sw_fini()
378 		if (adev->uvd.harvest_config & (1 << j))  in amdgpu_uvd_sw_fini()
380 		kvfree(adev->uvd.inst[j].saved_bo);  in amdgpu_uvd_sw_fini()
382 		amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,  in amdgpu_uvd_sw_fini()
383 				      &adev->uvd.inst[j].gpu_addr,  in amdgpu_uvd_sw_fini()
384 				      (void **)&adev->uvd.inst[j].cpu_addr);  in amdgpu_uvd_sw_fini()
386 		amdgpu_ring_fini(&adev->uvd.inst[j].ring);  in amdgpu_uvd_sw_fini()
389 			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);  in amdgpu_uvd_sw_fini()
391 	amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);  in amdgpu_uvd_sw_fini()
392 	amdgpu_ucode_release(&adev->uvd.fw);  in amdgpu_uvd_sw_fini()
409 	ring = &adev->uvd.inst[0].ring;  in amdgpu_uvd_entity_init()
411 	r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,  in amdgpu_uvd_entity_init()
428 	cancel_delayed_work_sync(&adev->uvd.idle_work);  in amdgpu_uvd_suspend()
432 		for (i = 0; i < adev->uvd.max_handles; ++i)  in amdgpu_uvd_suspend()
433 			if (atomic_read(&adev->uvd.handles[i]))  in amdgpu_uvd_suspend()
436 		if (i == adev->uvd.max_handles)  in amdgpu_uvd_suspend()
440 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {  in amdgpu_uvd_suspend()
441 		if (adev->uvd.harvest_config & (1 << j))  in amdgpu_uvd_suspend()
443 		if (adev->uvd.inst[j].vcpu_bo == NULL)  in amdgpu_uvd_suspend()
446 		size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);  in amdgpu_uvd_suspend()
447 		ptr = adev->uvd.inst[j].cpu_addr;  in amdgpu_uvd_suspend()
449 		adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);  in amdgpu_uvd_suspend()
450 		if (!adev->uvd.inst[j].saved_bo)  in amdgpu_uvd_suspend()
456 				memset(adev->uvd.inst[j].saved_bo, 0, size);  in amdgpu_uvd_suspend()
458 				memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);  in amdgpu_uvd_suspend()
476 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {  in amdgpu_uvd_resume()
477 		if (adev->uvd.harvest_config & (1 << i))  in amdgpu_uvd_resume()
479 		if (adev->uvd.inst[i].vcpu_bo == NULL)  in amdgpu_uvd_resume()
482 		size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);  in amdgpu_uvd_resume()
483 		ptr = adev->uvd.inst[i].cpu_addr;  in amdgpu_uvd_resume()
485 		if (adev->uvd.inst[i].saved_bo != NULL) {  in amdgpu_uvd_resume()
487 				memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);  in amdgpu_uvd_resume()
490 			kvfree(adev->uvd.inst[i].saved_bo);  in amdgpu_uvd_resume()
491 			adev->uvd.inst[i].saved_bo = NULL;  in amdgpu_uvd_resume()
496 			hdr = (const struct common_firmware_header *)adev->uvd.fw->data;  in amdgpu_uvd_resume()
500 					memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,  in amdgpu_uvd_resume()
509 			amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);  in amdgpu_uvd_resume()
517 	struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;  in amdgpu_uvd_free_handles()
520 	for (i = 0; i < adev->uvd.max_handles; ++i) {  in amdgpu_uvd_free_handles()
521 		uint32_t handle = atomic_read(&adev->uvd.handles[i]);  in amdgpu_uvd_free_handles()
523 		if (handle != 0 && adev->uvd.filp[i] == filp) {  in amdgpu_uvd_free_handles()
536 			adev->uvd.filp[i] = NULL;  in amdgpu_uvd_free_handles()
537 			atomic_set(&adev->uvd.handles[i], 0);  in amdgpu_uvd_free_handles()
587 	if (!ctx->parser->adev->uvd.address_64_bit) {  in amdgpu_uvd_cs_pass1()
747 		if (!adev->uvd.use_ctx_buf) {  in amdgpu_uvd_cs_msg_decode()
795 	adev->uvd.decode_image_width = width;  in amdgpu_uvd_cs_msg_decode()
846 		for (i = 0; i < adev->uvd.max_handles; ++i) {  in amdgpu_uvd_cs_msg()
847 			if (atomic_read(&adev->uvd.handles[i]) == handle) {  in amdgpu_uvd_cs_msg()
853 			if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {  in amdgpu_uvd_cs_msg()
854 				adev->uvd.filp[i] = ctx->parser->filp;  in amdgpu_uvd_cs_msg()
870 		for (i = 0; i < adev->uvd.max_handles; ++i) {  in amdgpu_uvd_cs_msg()
871 			if (atomic_read(&adev->uvd.handles[i]) == handle) {  in amdgpu_uvd_cs_msg()
872 				if (adev->uvd.filp[i] != ctx->parser->filp) {  in amdgpu_uvd_cs_msg()
885 		for (i = 0; i < adev->uvd.max_handles; ++i)  in amdgpu_uvd_cs_msg()
886 			atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);  in amdgpu_uvd_cs_msg()
952 	if (!ctx->parser->adev->uvd.address_64_bit) {  in amdgpu_uvd_cs_pass2()
960 		    (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {  in amdgpu_uvd_cs_pass2()
1099 	if (!parser->adev->uvd.address_64_bit) {  in amdgpu_uvd_ring_parse_cs()
1130 	r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,  in amdgpu_uvd_send_msg()
1198 	struct amdgpu_bo *bo = adev->uvd.ib_bo;  in amdgpu_uvd_get_create_msg()
1231 		bo = adev->uvd.ib_bo;  in amdgpu_uvd_get_destroy_msg()
1258 		container_of(work, struct amdgpu_device, uvd.idle_work.work);  in amdgpu_uvd_idle_work_handler()
1261 	for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {  in amdgpu_uvd_idle_work_handler()
1262 		if (adev->uvd.harvest_config & (1 << i))  in amdgpu_uvd_idle_work_handler()
1264 		fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);  in amdgpu_uvd_idle_work_handler()
1265 		for (j = 0; j < adev->uvd.num_enc_rings; ++j)  in amdgpu_uvd_idle_work_handler()
1266 			fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);  in amdgpu_uvd_idle_work_handler()
1281 		schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);  in amdgpu_uvd_idle_work_handler()
1293 	set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);  in amdgpu_uvd_ring_begin_use()
1310 		schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);  in amdgpu_uvd_ring_end_use()
1365 	for (i = 0; i < adev->uvd.max_handles; ++i) {  in amdgpu_uvd_used_handles()
1371 		if (atomic_read(&adev->uvd.handles[i]))  in amdgpu_uvd_used_handles()