91 		if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&  in amdgpu_umc_do_page_retirement()
92 		    adev->umc.ras->ras_block.hw_ops->query_ras_error_count)  in amdgpu_umc_do_page_retirement()
93 		    adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);  in amdgpu_umc_do_page_retirement()
95 		if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&  in amdgpu_umc_do_page_retirement()
96 		    adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&  in amdgpu_umc_do_page_retirement()
112 			adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status);  in amdgpu_umc_do_page_retirement()
225 	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);  in amdgpu_umc_ras_sw_init()
231 	strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");  in amdgpu_umc_ras_sw_init()
232 	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;  in amdgpu_umc_ras_sw_init()
233 	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in amdgpu_umc_ras_sw_init()
234 	adev->umc.ras_if = &ras->ras_block.ras_comm;  in amdgpu_umc_ras_sw_init()
236 	if (!ras->ras_block.ras_late_init)  in amdgpu_umc_ras_sw_init()
237 		ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;  in amdgpu_umc_ras_sw_init()
239 	if (!ras->ras_block.ras_cb)  in amdgpu_umc_ras_sw_init()
240 		ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;  in amdgpu_umc_ras_sw_init()
245 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)  in amdgpu_umc_ras_late_init()  argument
249 	r = amdgpu_ras_block_late_init(adev, ras_block);  in amdgpu_umc_ras_late_init()
253 	if (amdgpu_ras_is_supported(adev, ras_block->block)) {  in amdgpu_umc_ras_late_init()
267 	amdgpu_ras_block_late_fini(adev, ras_block);  in amdgpu_umc_ras_late_init()