Lines Matching refs:adev
38 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_enter_safe_mode() argument
40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
47 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id) in amdgpu_gfx_rlc_exit_safe_mode() argument
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
72 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
89 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws) in amdgpu_gfx_rlc_init_sr() argument
97 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, in amdgpu_gfx_rlc_init_sr()
100 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
101 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
102 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_init_sr()
104 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); in amdgpu_gfx_rlc_init_sr()
105 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_sr()
110 src_ptr = adev->gfx.rlc.reg_list; in amdgpu_gfx_rlc_init_sr()
111 dst_ptr = adev->gfx.rlc.sr_ptr; in amdgpu_gfx_rlc_init_sr()
112 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in amdgpu_gfx_rlc_init_sr()
114 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
115 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
128 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_csb() argument
134 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
135 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE, in amdgpu_gfx_rlc_init_csb()
138 &adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_init_csb()
139 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
140 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_init_csb()
142 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", r); in amdgpu_gfx_rlc_init_csb()
143 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_csb()
158 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_cpt() argument
162 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in amdgpu_gfx_rlc_init_cpt()
165 &adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_init_cpt()
166 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_init_cpt()
167 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_init_cpt()
169 dev_err(adev->dev, "(%d) failed to create cp table bo\n", r); in amdgpu_gfx_rlc_init_cpt()
170 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_cpt()
175 amdgpu_gfx_rlc_setup_cp_table(adev); in amdgpu_gfx_rlc_init_cpt()
176 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
177 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
189 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev) in amdgpu_gfx_rlc_setup_cp_table() argument
197 max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev); in amdgpu_gfx_rlc_setup_cp_table()
200 dst_ptr = adev->gfx.rlc.cp_table_ptr; in amdgpu_gfx_rlc_setup_cp_table()
204 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
206 (adev->gfx.ce_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
212 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
214 (adev->gfx.pfp_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
220 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
222 (adev->gfx.me_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
228 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
230 (adev->gfx.mec_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
236 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
238 (adev->gfx.mec2_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
261 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev) in amdgpu_gfx_rlc_fini() argument
264 if (adev->gfx.rlc.save_restore_obj) { in amdgpu_gfx_rlc_fini()
265 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_fini()
266 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_fini()
267 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_fini()
271 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_fini()
272 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
273 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_fini()
276 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_fini()
277 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_fini()
278 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_fini()
281 static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_0() argument
289 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_0()
291 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_0()
292 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_0()
293 adev->gfx.rlc.save_and_restore_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
295 adev->gfx.rlc.clear_state_descriptor_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
297 adev->gfx.rlc.avail_scratch_ram_locations = in amdgpu_gfx_rlc_init_microcode_v2_0()
299 adev->gfx.rlc.reg_restore_list_size = in amdgpu_gfx_rlc_init_microcode_v2_0()
301 adev->gfx.rlc.reg_list_format_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
303 adev->gfx.rlc.reg_list_format_separate_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
305 adev->gfx.rlc.starting_offsets_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
307 adev->gfx.rlc.reg_list_format_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
309 adev->gfx.rlc.reg_list_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
311 adev->gfx.rlc.register_list_format = in amdgpu_gfx_rlc_init_microcode_v2_0()
312 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in amdgpu_gfx_rlc_init_microcode_v2_0()
313 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in amdgpu_gfx_rlc_init_microcode_v2_0()
314 if (!adev->gfx.rlc.register_list_format) { in amdgpu_gfx_rlc_init_microcode_v2_0()
315 dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n"); in amdgpu_gfx_rlc_init_microcode_v2_0()
322 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
324 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in amdgpu_gfx_rlc_init_microcode_v2_0()
329 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
331 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_0()
332 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in amdgpu_gfx_rlc_init_microcode_v2_0()
334 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_0()
337 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_0()
345 static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_1() argument
350 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_1()
351 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
352 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
353 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in amdgpu_gfx_rlc_init_microcode_v2_1()
354 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in amdgpu_gfx_rlc_init_microcode_v2_1()
355 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
356 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
357 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
358 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
359 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
360 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
361 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
362 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
363 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in amdgpu_gfx_rlc_init_microcode_v2_1()
366 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_1()
367 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
368 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; in amdgpu_gfx_rlc_init_microcode_v2_1()
370 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
371 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
372 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
375 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
376 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
378 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
379 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
380 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
383 if (adev->gfx.rlc.save_restore_list_srm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
384 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
386 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
387 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
388 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
393 static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_2() argument
398 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_2()
399 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
400 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
401 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
402 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
404 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_2()
405 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
406 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
408 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_2()
409 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_2()
410 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
413 if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
414 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
416 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_2()
417 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_2()
418 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
423 static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_3() argument
428 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_3()
429 adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
430 adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
431 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
432 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
434 adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
435 adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
436 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
437 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
439 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_3()
440 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
441 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; in amdgpu_gfx_rlc_init_microcode_v2_3()
443 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_3()
444 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_3()
445 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
448 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
449 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; in amdgpu_gfx_rlc_init_microcode_v2_3()
451 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_3()
452 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_3()
453 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
458 static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_4() argument
463 rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_4()
464 …adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_si… in amdgpu_gfx_rlc_init_microcode_v2_4()
465 …adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_uco… in amdgpu_gfx_rlc_init_microcode_v2_4()
466 …adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
467 …adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
468 …adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
469 …adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
470 …adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
471 …adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
472 …adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
473 …adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
475 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_4()
476 if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
477 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
479 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
480 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
481 ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
484 if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
485 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
487 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
488 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
489 ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
492 if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
493 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
495 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
496 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
497 ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
500 if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
501 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
503 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
504 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
505 ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
508 if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
509 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
511 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
512 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
513 ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
518 int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev, in amdgpu_gfx_rlc_init_microcode() argument
526 dev_err(adev->dev, "unsupported rlc fw hdr\n"); in amdgpu_gfx_rlc_init_microcode()
532 adev->gfx.rlc.is_rlc_v2_1 = true; in amdgpu_gfx_rlc_init_microcode()
535 err = amdgpu_gfx_rlc_init_microcode_v2_0(adev); in amdgpu_gfx_rlc_init_microcode()
537 dev_err(adev->dev, "fail to init rlc v2_0 microcode\n"); in amdgpu_gfx_rlc_init_microcode()
542 amdgpu_gfx_rlc_init_microcode_v2_1(adev); in amdgpu_gfx_rlc_init_microcode()
544 amdgpu_gfx_rlc_init_microcode_v2_2(adev); in amdgpu_gfx_rlc_init_microcode()
546 amdgpu_gfx_rlc_init_microcode_v2_3(adev); in amdgpu_gfx_rlc_init_microcode()
548 amdgpu_gfx_rlc_init_microcode_v2_4(adev); in amdgpu_gfx_rlc_init_microcode()