214 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr)  in amdgpu_ring_mux_set_wptr()  argument
240 	e->sw_wptr = wptr;  in amdgpu_ring_mux_set_wptr()
241 	e->start_ptr_in_hw_ring = mux->real_ring->wptr;  in amdgpu_ring_mux_set_wptr()
244 	if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) {  in amdgpu_ring_mux_set_wptr()
245 		amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr);  in amdgpu_ring_mux_set_wptr()
246 		e->end_ptr_in_hw_ring = mux->real_ring->wptr;  in amdgpu_ring_mux_set_wptr()
249 		e->end_ptr_in_hw_ring = mux->real_ring->wptr;  in amdgpu_ring_mux_set_wptr()
341 	amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr);  in amdgpu_sw_ring_set_wptr_gfx()
429 	offset = ring->wptr & ring->buf_mask;  in amdgpu_sw_ring_ib_mark_offset()
455 	chunk->start = ring->wptr;  in amdgpu_ring_mux_start_ib()
537 	chunk->end = ring->wptr;  in amdgpu_ring_mux_end_ib()