89 	/* Direct submission to the ring buffer during init and reset. */
114 	/* sync_seq is protected by ring emission lock */
128 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
129 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
130 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
132 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
133 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
140 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
142 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
144 bool amdgpu_fence_process(struct amdgpu_ring *ring);
145 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
146 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
149 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
153 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
154 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
161 /* provided by hw blocks that expose a ring buffer for commands */
171 	/* ring read/write ptr handling */
172 	u64 (*get_rptr)(struct amdgpu_ring *ring);
173 	u64 (*get_wptr)(struct amdgpu_ring *ring);
174 	void (*set_wptr)(struct amdgpu_ring *ring);
186 	void (*emit_ib)(struct amdgpu_ring *ring,
190 	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
192 	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
193 	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
195 	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
196 	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
201 	int (*test_ring)(struct amdgpu_ring *ring);
202 	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
204 	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
205 	void (*insert_start)(struct amdgpu_ring *ring);
206 	void (*insert_end)(struct amdgpu_ring *ring);
208 	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
209 	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
210 	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
212 	void (*begin_use)(struct amdgpu_ring *ring);
213 	void (*end_use)(struct amdgpu_ring *ring);
214 	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
215 	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
216 	void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
218 	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
220 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
221 	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
223 	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
226 	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
228 	/* Try to soft recover the ring to make the fence signal */
229 	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
230 	int (*preempt_ib)(struct amdgpu_ring *ring);
231 	void (*emit_mem_sync)(struct amdgpu_ring *ring);
232 	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
233 	void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
234 	void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
235 	void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
245 	volatile uint32_t	*ring;  member
335 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
336 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
337 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
338 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
339 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
340 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
342 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
343 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
344 void amdgpu_ring_commit(struct amdgpu_ring *ring);
345 void amdgpu_ring_undo(struct amdgpu_ring *ring);
346 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
350 void amdgpu_ring_fini(struct amdgpu_ring *ring);
351 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
354 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
357 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,  in amdgpu_ring_set_preempt_cond_exec()  argument
360 	*ring->cond_exe_cpu_addr = cond_exec;  in amdgpu_ring_set_preempt_cond_exec()
363 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)  in amdgpu_ring_clear_ring()  argument
366 	while (i <= ring->buf_mask)  in amdgpu_ring_clear_ring()
367 		ring->ring[i++] = ring->funcs->nop;  in amdgpu_ring_clear_ring()
371 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)  in amdgpu_ring_write()  argument
373 	if (ring->count_dw <= 0)  in amdgpu_ring_write()
374 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");  in amdgpu_ring_write()
375 	ring->ring[ring->wptr++ & ring->buf_mask] = v;  in amdgpu_ring_write()
376 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write()
377 	ring->count_dw--;  in amdgpu_ring_write()
380 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,  in amdgpu_ring_write_multiple()  argument
386 	if (unlikely(ring->count_dw < count_dw))  in amdgpu_ring_write_multiple()
387 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");  in amdgpu_ring_write_multiple()
389 	occupied = ring->wptr & ring->buf_mask;  in amdgpu_ring_write_multiple()
390 	dst = (void *)&ring->ring[occupied];  in amdgpu_ring_write_multiple()
391 	chunk1 = ring->buf_mask + 1 - occupied;  in amdgpu_ring_write_multiple()
402 		dst = (void *)ring->ring;  in amdgpu_ring_write_multiple()
406 	ring->wptr += count_dw;  in amdgpu_ring_write_multiple()
407 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write_multiple()
408 	ring->count_dw -= count_dw;  in amdgpu_ring_write_multiple()
411 #define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)			\  argument
412 	(ring->is_mes_queue && ring->mes_ctx ?				\
413 	 (ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
415 #define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)			\  argument
416 	(ring->is_mes_queue && ring->mes_ctx ?				\
417 	 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
420 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
423 			      struct amdgpu_ring *ring);
425 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
444 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,