128  * add to control->i2c_address, and then tell I2C layer to read
171 				  struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr()  argument
176 	if (!control)  in __get_eeprom_i2c_addr()
189 		control->i2c_address = ((u32) i2c_addr) << 16;  in __get_eeprom_i2c_addr()
198 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
202 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
204 			control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
207 		control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
212 			control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
214 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
219 		control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
252 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)  in __write_table_header()  argument
255 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_header()
259 	__encode_table_header_to_buf(&control->tbl_hdr, buf);  in __write_table_header()
264 				  control->i2c_address +  in __write_table_header()
265 				  control->ras_header_offset,  in __write_table_header()
308 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)  in __write_table_ras_info()  argument
310 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_ras_info()
320 	__encode_table_ras_info_to_buf(&control->tbl_rai, buf);  in __write_table_ras_info()
325 				  control->i2c_address +  in __write_table_ras_info()
326 				  control->ras_info_offset,  in __write_table_ras_info()
345 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
352 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);  in __calc_hdr_byte_sum()
353 	pp = (u8 *) &control->tbl_hdr;  in __calc_hdr_byte_sum()
361 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_ras_info_byte_sum()  argument
367 	sz = sizeof(control->tbl_rai);  in __calc_ras_info_byte_sum()
368 	pp = (u8 *) &control->tbl_rai;  in __calc_ras_info_byte_sum()
377 	struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_correct_header_tag()  argument
380 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_correct_header_tag()
392 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
395 	res = __write_table_header(control);  in amdgpu_ras_eeprom_correct_header_tag()
396 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
403  * @control: pointer to control structure
408 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_reset_table()  argument
410 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_reset_table()
411 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_reset_table()
412 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;  in amdgpu_ras_eeprom_reset_table()
417 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
443 	csum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
445 		csum += __calc_ras_info_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
448 	res = __write_table_header(control);  in amdgpu_ras_eeprom_reset_table()
450 		res = __write_table_ras_info(control);  in amdgpu_ras_eeprom_reset_table()
452 	control->ras_num_recs = 0;  in amdgpu_ras_eeprom_reset_table()
453 	control->ras_fri = 0;  in amdgpu_ras_eeprom_reset_table()
455 	amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);  in amdgpu_ras_eeprom_reset_table()
457 	control->bad_channel_bitmap = 0;  in amdgpu_ras_eeprom_reset_table()
458 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);  in amdgpu_ras_eeprom_reset_table()
461 	amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_reset_table()
463 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
469 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buf()  argument
497 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buf()  argument
559  * @control: pointer to control structure
564  * The caller must hold the table mutex in @control.
567 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_write()  argument
570 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_write()
578 				  control->i2c_address +  in __amdgpu_ras_eeprom_write()
579 				  RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_write()
599 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append_table()  argument
603 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));  in amdgpu_ras_eeprom_append_table()
616 		__encode_table_record_to_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_append_table()
619 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_append_table()
620 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_append_table()
629 	 * Let N = control->ras_max_num_record_count, then we have,  in amdgpu_ras_eeprom_append_table()
652 	a = control->ras_fri + control->ras_num_recs;  in amdgpu_ras_eeprom_append_table()
654 	if (b < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
655 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
656 	} else if (a < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
659 		g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
660 		g1 = b % control->ras_max_record_count + 1;  in amdgpu_ras_eeprom_append_table()
661 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
664 		res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
669 		if (g1 > control->ras_fri)  in amdgpu_ras_eeprom_append_table()
670 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
672 		a %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
673 		b %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
677 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
680 			if (b >= control->ras_fri)  in amdgpu_ras_eeprom_append_table()
681 				control->ras_fri = (b + 1) % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
689 			g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
691 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
694 			res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
699 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
702 	control->ras_num_recs = 1 + (control->ras_max_record_count + b  in amdgpu_ras_eeprom_append_table()
703 				     - control->ras_fri)  in amdgpu_ras_eeprom_append_table()
704 		% control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
711 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_update_header()  argument
713 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_update_header()
722 	    control->ras_num_recs >= ras->bad_page_cnt_threshold) {  in amdgpu_ras_eeprom_update_header()
725 			control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_update_header()
726 		control->tbl_hdr.header = RAS_TABLE_HDR_BAD;  in amdgpu_ras_eeprom_update_header()
727 		if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) {  in amdgpu_ras_eeprom_update_header()
728 			control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;  in amdgpu_ras_eeprom_update_header()
729 			control->tbl_rai.health_percent = 0;  in amdgpu_ras_eeprom_update_header()
733 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_update_header()
734 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_update_header()
736 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
738 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_update_header()
739 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
740 	control->tbl_hdr.checksum = 0;  in amdgpu_ras_eeprom_update_header()
742 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
743 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);  in amdgpu_ras_eeprom_update_header()
746 			  control->tbl_hdr.tbl_size);  in amdgpu_ras_eeprom_update_header()
753 				 control->i2c_address +  in amdgpu_ras_eeprom_update_header()
754 				 control->ras_record_offset,  in amdgpu_ras_eeprom_update_header()
773 	    control->tbl_hdr.version == RAS_TABLE_VER_V2_1 &&  in amdgpu_ras_eeprom_update_header()
774 	    control->ras_num_recs < ras->bad_page_cnt_threshold)  in amdgpu_ras_eeprom_update_header()
775 		control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -  in amdgpu_ras_eeprom_update_header()
776 						   control->ras_num_recs) * 100) /  in amdgpu_ras_eeprom_update_header()
785 	csum += __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
786 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_update_header()
787 		csum += __calc_ras_info_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
790 	control->tbl_hdr.checksum = csum;  in amdgpu_ras_eeprom_update_header()
791 	res = __write_table_header(control);  in amdgpu_ras_eeprom_update_header()
792 	if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)  in amdgpu_ras_eeprom_update_header()
793 		res = __write_table_ras_info(control);  in amdgpu_ras_eeprom_update_header()
801  * @control: pointer to control structure
807  * can be appended is between 1 and control->ras_max_record_count,
812 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append()  argument
816 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_append()
825 	} else if (num > control->ras_max_record_count) {  in amdgpu_ras_eeprom_append()
827 			  num, control->ras_max_record_count);  in amdgpu_ras_eeprom_append()
831 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
833 	res = amdgpu_ras_eeprom_append_table(control, record, num);  in amdgpu_ras_eeprom_append()
835 		res = amdgpu_ras_eeprom_update_header(control);  in amdgpu_ras_eeprom_append()
837 		amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_append()
839 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
845  * @control: pointer to control structure
850  * The caller must hold the table mutex in @control.
853 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_read()  argument
856 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_read()
864 				 control->i2c_address +  in __amdgpu_ras_eeprom_read()
865 				 RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_read()
886  * @control: pointer to control structure
895 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_read()  argument
899 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_read()
911 	} else if (num > control->ras_num_recs) {  in amdgpu_ras_eeprom_read()
913 			  num, control->ras_num_recs);  in amdgpu_ras_eeprom_read()
941 	g0 = control->ras_fri + num - 1;  in amdgpu_ras_eeprom_read()
942 	g1 = g0 % control->ras_max_record_count;  in amdgpu_ras_eeprom_read()
943 	if (g0 < control->ras_max_record_count) {  in amdgpu_ras_eeprom_read()
947 		g0 = control->ras_max_record_count - control->ras_fri;  in amdgpu_ras_eeprom_read()
951 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
952 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);  in amdgpu_ras_eeprom_read()
956 		res = __amdgpu_ras_eeprom_read(control,  in amdgpu_ras_eeprom_read()
969 		__decode_table_record_from_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_read()
972 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_read()
973 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_read()
979 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
984 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_max_record_count()  argument
986 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_max_record_count()
998 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_size_read()  local
1005 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_size_read()
1009 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);  in amdgpu_ras_debugfs_eeprom_size_read()
1046 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_table_size()  argument
1049 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;  in amdgpu_ras_debugfs_table_size()
1052 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_set_ret_size()  argument
1054 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,  in amdgpu_ras_debugfs_set_ret_size()
1059 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_set_ret_size()
1067 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;  in amdgpu_ras_debugfs_table_read()  local
1072 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
1094 			 control->tbl_hdr.header,  in amdgpu_ras_debugfs_table_read()
1095 			 control->tbl_hdr.version,  in amdgpu_ras_debugfs_table_read()
1096 			 control->tbl_hdr.first_rec_offset,  in amdgpu_ras_debugfs_table_read()
1097 			 control->tbl_hdr.tbl_size,  in amdgpu_ras_debugfs_table_read()
1098 			 control->tbl_hdr.checksum);  in amdgpu_ras_debugfs_table_read()
1124 	data_len = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_table_read()
1140 		for ( ; size > 0 && s < control->ras_num_recs; s++) {  in amdgpu_ras_debugfs_table_read()
1141 			u32 ai = RAS_RI_TO_AI(control, s);  in amdgpu_ras_debugfs_table_read()
1144 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);  in amdgpu_ras_debugfs_table_read()
1147 			__decode_table_record_from_buf(control, &record, dare);  in amdgpu_ras_debugfs_table_read()
1150 				 RAS_INDEX_TO_OFFSET(control, ai),  in amdgpu_ras_debugfs_table_read()
1172 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
1182 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_table_read()  local
1189 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_table_read()
1217  * @control: pointer to control structure
1225 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)  in __verify_ras_table_checksum()  argument
1227 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __verify_ras_table_checksum()
1231 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in __verify_ras_table_checksum()
1234 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1237 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1246 				 control->i2c_address +  in __verify_ras_table_checksum()
1247 				 control->ras_header_offset,  in __verify_ras_table_checksum()
1266 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)  in __read_table_ras_info()  argument
1268 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;  in __read_table_ras_info()
1269 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __read_table_ras_info()
1284 				 control->i2c_address + control->ras_info_offset,  in __read_table_ras_info()
1299 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_init()  argument
1302 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
1304 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
1317 	if (!__get_eeprom_i2c_addr(adev, control))  in amdgpu_ras_eeprom_init()
1320 	control->ras_header_offset = RAS_HDR_START;  in amdgpu_ras_eeprom_init()
1321 	control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;  in amdgpu_ras_eeprom_init()
1322 	mutex_init(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_init()
1326 				 control->i2c_address + control->ras_header_offset,  in amdgpu_ras_eeprom_init()
1336 		control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);  in amdgpu_ras_eeprom_init()
1337 		control->ras_record_offset = RAS_RECORD_START_V2_1;  in amdgpu_ras_eeprom_init()
1338 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;  in amdgpu_ras_eeprom_init()
1340 		control->ras_num_recs = RAS_NUM_RECS(hdr);  in amdgpu_ras_eeprom_init()
1341 		control->ras_record_offset = RAS_RECORD_START;  in amdgpu_ras_eeprom_init()
1342 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT;  in amdgpu_ras_eeprom_init()
1344 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);  in amdgpu_ras_eeprom_init()
1348 				 control->ras_num_recs);  in amdgpu_ras_eeprom_init()
1351 			res = __read_table_ras_info(control);  in amdgpu_ras_eeprom_init()
1356 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1363 		if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)  in amdgpu_ras_eeprom_init()
1365 					control->ras_num_recs,  in amdgpu_ras_eeprom_init()
1370 			res = __read_table_ras_info(control);  in amdgpu_ras_eeprom_init()
1375 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1379 		if (ras->bad_page_cnt_threshold > control->ras_num_recs) {  in amdgpu_ras_eeprom_init()
1382 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,  in amdgpu_ras_eeprom_init()
1389 				 control->ras_num_recs,  in amdgpu_ras_eeprom_init()
1391 			res = amdgpu_ras_eeprom_correct_header_tag(control,  in amdgpu_ras_eeprom_init()
1395 				control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_init()
1404 					control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_init()
1410 		res = amdgpu_ras_eeprom_reset_table(control);  in amdgpu_ras_eeprom_init()