Lines Matching refs:xcc_id

286 			     u32 sh_num, u32 instance, int xcc_id);
287 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
289 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
292 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
296 				 u32 queue, u32 vmid, u32 xcc_id);
458 …elect_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (…  argument
459 …_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe)…  argument
481 			     struct amdgpu_irq_src *irq, int xcc_id);
485 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
487 			unsigned hpd_size, int xcc_id);
490 			   unsigned mqd_size, int xcc_id);
491 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
492 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
493 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
494 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
495 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
504 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
538 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
544 				int xcc_id));