Lines Matching refs:amdgpu_device

266 	void (*enable_watchdog_timer)(struct amdgpu_device *adev);
267 	bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
268 	int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
271 	int (*poison_consumption_handler)(struct amdgpu_device *adev,
284 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
285 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
287 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
289 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
292 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
295 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
297 	void (*init_spm_golden)(struct amdgpu_device *adev);
298 	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
299 	int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
302 			(*query_partition_mode)(struct amdgpu_device *adev);
303 	int (*switch_partition_mode)(struct amdgpu_device *adev,
305 	int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node);
479 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
485 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
486 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
489 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
491 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
492 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
493 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
494 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);
495 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id);
497 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
498 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
500 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
502 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
504 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
506 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
508 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
510 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
512 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
514 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
516 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
517 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
518 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
519 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
520 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
521 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
522 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
523 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
526 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
529 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
530 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
531 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
532 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
534 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
535 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
538 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);
539 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev);
540 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev);
541 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
543 		void (*func)(struct amdgpu_device *adev, void *ras_error_status,