Lines Matching refs:modifier
655 amdgpu_lookup_format_info(u32 format, uint64_t modifier) in amdgpu_lookup_format_info() argument
657 if (!IS_AMD_FMT_MOD(modifier)) in amdgpu_lookup_format_info()
660 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) in amdgpu_lookup_format_info()
665 if (AMD_FMT_MOD_GET(DCC, modifier)) in amdgpu_lookup_format_info()
727 uint64_t modifier = 0; in convert_tiling_flags_to_modifier() local
735 modifier = DRM_FORMAT_MOD_LINEAR; in convert_tiling_flags_to_modifier()
827 modifier = AMD_FMT_MOD | in convert_tiling_flags_to_modifier()
850 modifier |= AMD_FMT_MOD_SET(DCC, 1) | in convert_tiling_flags_to_modifier()
875 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); in convert_tiling_flags_to_modifier()
887 modifier |= AMD_FMT_MOD_SET(RB, rb) | in convert_tiling_flags_to_modifier()
897 modifier); in convert_tiling_flags_to_modifier()
905 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
944 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, in get_dcc_block_size() argument
947 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); in get_dcc_block_size()
956 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); in get_dcc_block_size()
961 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); in get_dcc_block_size()
964 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) in get_dcc_block_size()
1028 uint64_t modifier = rfb->base.modifier; in amdgpu_display_verify_sizes() local
1036 if (modifier == DRM_FORMAT_MOD_LINEAR) { in amdgpu_display_verify_sizes()
1041 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes()
1075 if (AMD_FMT_MOD_GET(DCC, modifier)) { in amdgpu_display_verify_sizes()
1076 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { in amdgpu_display_verify_sizes()
1077 block_size_log2 = get_dcc_block_size(modifier, false, false); in amdgpu_display_verify_sizes()
1087 block_size_log2 = get_dcc_block_size(modifier, true, true); in amdgpu_display_verify_sizes()
1089 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); in amdgpu_display_verify_sizes()
1091 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); in amdgpu_display_verify_sizes()
1149 mode_cmd->modifier[0])) { in amdgpu_display_gem_fb_verify_and_init()
1152 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in amdgpu_display_gem_fb_verify_and_init()