95 } ichx_priv;  variable
108 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_write_bit()
110 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
111 		data = ichx_priv.outlvl_cache[reg_nr];  in ichx_write_bit()
113 		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
114 				 ichx_priv.gpio_base);  in ichx_write_bit()
120 	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
121 			 ichx_priv.gpio_base);  in ichx_write_bit()
122 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
123 		ichx_priv.outlvl_cache[reg_nr] = data;  in ichx_write_bit()
125 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
126 			ichx_priv.gpio_base);  in ichx_write_bit()
128 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_write_bit()
140 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_read_bit()
142 	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_read_bit()
143 			 ichx_priv.gpio_base);  in ichx_read_bit()
145 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_read_bit()
146 		data = ichx_priv.outlvl_cache[reg_nr] | data;  in ichx_read_bit()
148 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_read_bit()
155 	return !!(ichx_priv.use_gpio & BIT(nr / 32));  in ichx_gpio_check_available()
179 	if (nr < 32 && ichx_priv.desc->have_blink)  in ichx_gpio_direction_output()
207 		if (!ichx_priv.pm_base)  in ich6_gpio_get()
210 		spin_lock_irqsave(&ichx_priv.lock, flags);  in ich6_gpio_get()
213 		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);  in ich6_gpio_get()
214 		data = ICHX_READ(0, ichx_priv.pm_base);  in ich6_gpio_get()
216 		spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ich6_gpio_get()
235 	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))  in ichx_gpio_request()
264 	chip->parent = ichx_priv.dev;  in ichx_gpiolib_setup()
267 	chip->request = ichx_priv.desc->request ?  in ichx_gpiolib_setup()
268 		ichx_priv.desc->request : ichx_gpio_request;  in ichx_gpiolib_setup()
269 	chip->get = ichx_priv.desc->get ?  in ichx_gpiolib_setup()
270 		ichx_priv.desc->get : ichx_gpio_get;  in ichx_gpiolib_setup()
277 	chip->ngpio = ichx_priv.desc->ngpio;  in ichx_gpiolib_setup()
374 	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {  in ichx_gpio_request_regions()
378 				res_base->start + ichx_priv.desc->regs[0][i],  in ichx_gpio_request_regions()
379 				ichx_priv.desc->reglen[i], name))  in ichx_gpio_request_regions()
397 		ichx_priv.desc = &i3100_desc;  in ichx_gpio_probe()
400 		ichx_priv.desc = &intel5_desc;  in ichx_gpio_probe()
403 		ichx_priv.desc = &ich6_desc;  in ichx_gpio_probe()
406 		ichx_priv.desc = &ich7_desc;  in ichx_gpio_probe()
409 		ichx_priv.desc = &ich9_desc;  in ichx_gpio_probe()
412 		ichx_priv.desc = &ich10_corp_desc;  in ichx_gpio_probe()
415 		ichx_priv.desc = &ich10_cons_desc;  in ichx_gpio_probe()
418 		ichx_priv.desc = &avoton_desc;  in ichx_gpio_probe()
424 	ichx_priv.dev = dev;  in ichx_gpio_probe()
425 	spin_lock_init(&ichx_priv.lock);  in ichx_gpio_probe()
433 	ichx_priv.gpio_base = res_base;  in ichx_gpio_probe()
434 	ichx_priv.use_gpio = ich_info->use_gpio;  in ichx_gpio_probe()
441 	if (!ichx_priv.desc->uses_gpe0)  in ichx_gpio_probe()
456 	ichx_priv.pm_base = res_pm;  in ichx_gpio_probe()
459 	ichx_gpiolib_setup(&ichx_priv.chip);  in ichx_gpio_probe()
460 	err = devm_gpiochip_add_data(dev, &ichx_priv.chip, NULL);  in ichx_gpio_probe()
466 	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,  in ichx_gpio_probe()
467 		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);  in ichx_gpio_probe()