63 	int			irqs[MAX_INT_PER_BANK];  member
237 		chips->irqs[i] = platform_get_irq(pdev, i);  in davinci_gpio_probe()
238 		if (chips->irqs[i] < 0)  in davinci_gpio_probe()
239 			return chips->irqs[i];  in davinci_gpio_probe()
277  * We expect irqs will normally be set up as input pins, but they can also be
352 		/* ack any irqs */  in gpio_irq_handler()
390 	 * NOTE:  we assume for now that only irqs in the first gpio_chip  in gpio_to_irq_unbanked()
391 	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).  in gpio_to_irq_unbanked()
394 		return d->irqs[offset];  in gpio_to_irq_unbanked()
408 		if (data->irq == d->irqs[i])  in gpio_irq_type_unbanked()
534 	 * Arrange gpiod_to_irq() support, handling either direct IRQs or  in davinci_gpio_irq_setup()
535 	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct  in davinci_gpio_irq_setup()
536 	 * IRQs, while the others use banked IRQs, would need some setup  in davinci_gpio_irq_setup()
543 	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO  in davinci_gpio_irq_setup()
548 		/* pass "bank 0" GPIO IRQs to AINTC */  in davinci_gpio_irq_setup()
554 		irq = chips->irqs[0];  in davinci_gpio_irq_setup()
564 		/* set the direct IRQs up to use that irqchip */  in davinci_gpio_irq_setup()
566 			irq_set_chip(chips->irqs[gpio], irq_chip);  in davinci_gpio_irq_setup()
567 			irq_set_handler_data(chips->irqs[gpio], chips);  in davinci_gpio_irq_setup()
568 			irq_set_status_flags(chips->irqs[gpio],  in davinci_gpio_irq_setup()
576 	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we  in davinci_gpio_irq_setup()
590 		 * gpio irqs. Pass the irq bank's corresponding controller to  in davinci_gpio_irq_setup()
606 		irq_set_chained_handler_and_data(chips->irqs[bank],  in davinci_gpio_irq_setup()