Lines Matching +full:irq +full:- +full:can +full:- +full:wake
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015-2017 Broadcom
61 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
67 return bank->parent_priv; in brcmstb_gpio_gc_to_priv()
73 void __iomem *reg_base = bank->parent_priv->reg_base; in __brcmstb_gpio_get_active_irqs()
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & in __brcmstb_gpio_get_active_irqs()
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); in __brcmstb_gpio_get_active_irqs()
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); in brcmstb_gpio_hwirq_to_offset()
101 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_set_imask()
102 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_set_imask()
107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in brcmstb_gpio_set_imask()
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in brcmstb_gpio_set_imask()
121 int hwirq = offset + (gc->base - priv->gpio_base); in brcmstb_gpio_to_irq()
123 if (hwirq >= priv->num_gpios) in brcmstb_gpio_to_irq()
124 return -ENXIO; in brcmstb_gpio_to_irq()
125 return irq_create_mapping(priv->irq_domain, hwirq); in brcmstb_gpio_to_irq()
128 /* -------------------- IRQ chip functions -------------------- */
135 brcmstb_gpio_set_imask(bank, d->hwirq, false); in brcmstb_gpio_irq_mask()
143 brcmstb_gpio_set_imask(bank, d->hwirq, true); in brcmstb_gpio_irq_unmask()
150 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_ack()
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_ack()
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); in brcmstb_gpio_irq_ack()
160 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_type()
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_type()
194 return -EINVAL; in brcmstb_gpio_irq_set_type()
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
199 iedge_config = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
200 GIO_EC(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
202 GIO_EI(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
203 ilevel = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
204 GIO_LEVEL(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
223 ret = enable_irq_wake(priv->parent_wake_irq); in brcmstb_gpio_priv_set_wake()
225 ret = disable_irq_wake(priv->parent_wake_irq); in brcmstb_gpio_priv_set_wake()
227 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", in brcmstb_gpio_priv_set_wake()
236 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_wake()
237 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_wake()
244 bank->wake_active |= mask; in brcmstb_gpio_irq_set_wake()
246 bank->wake_active &= ~mask; in brcmstb_gpio_irq_set_wake()
251 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data) in brcmstb_gpio_wake_irq_handler() argument
255 if (!priv || irq != priv->parent_wake_irq) in brcmstb_gpio_wake_irq_handler()
264 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_bank_handler()
265 struct irq_domain *domain = priv->irq_domain; in brcmstb_gpio_irq_bank_handler()
266 int hwbase = bank->gc.base - priv->gpio_base; in brcmstb_gpio_irq_bank_handler()
273 if (offset >= bank->width) in brcmstb_gpio_irq_bank_handler()
274 dev_warn(&priv->pdev->dev, in brcmstb_gpio_irq_bank_handler()
275 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", in brcmstb_gpio_irq_bank_handler()
276 bank->id, offset); in brcmstb_gpio_irq_bank_handler()
282 /* Each UPG GIO block has one IRQ for all banks */
293 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_irq_handler()
305 list_for_each_entry_reverse(bank, &priv->bank_list, node) { in brcmstb_gpio_hwirq_to_bank()
306 i += bank->gc.ngpio; in brcmstb_gpio_hwirq_to_bank()
321 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq, in brcmstb_gpio_irq_map() argument
324 struct brcmstb_gpio_priv *priv = d->host_data; in brcmstb_gpio_irq_map()
327 struct platform_device *pdev = priv->pdev; in brcmstb_gpio_irq_map()
331 return -EINVAL; in brcmstb_gpio_irq_map()
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", in brcmstb_gpio_irq_map()
334 irq, (int)hwirq, bank->id); in brcmstb_gpio_irq_map()
335 ret = irq_set_chip_data(irq, &bank->gc); in brcmstb_gpio_irq_map()
338 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, in brcmstb_gpio_irq_map()
340 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq); in brcmstb_gpio_irq_map()
341 irq_set_noprobe(irq); in brcmstb_gpio_irq_map()
345 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) in brcmstb_gpio_irq_unmap() argument
347 irq_set_chip_and_handler(irq, NULL, NULL); in brcmstb_gpio_irq_unmap()
348 irq_set_chip_data(irq, NULL); in brcmstb_gpio_irq_unmap()
363 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); in brcmstb_gpio_sanity_check_banks()
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", in brcmstb_gpio_sanity_check_banks()
368 return -EINVAL; in brcmstb_gpio_sanity_check_banks()
380 if (priv->parent_irq > 0) in brcmstb_gpio_remove()
381 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL); in brcmstb_gpio_remove()
383 /* Remove all IRQ mappings and delete the domain */ in brcmstb_gpio_remove()
384 if (priv->irq_domain) { in brcmstb_gpio_remove()
385 for (offset = 0; offset < priv->num_gpios; offset++) { in brcmstb_gpio_remove()
386 virq = irq_find_mapping(priv->irq_domain, offset); in brcmstb_gpio_remove()
389 irq_domain_remove(priv->irq_domain); in brcmstb_gpio_remove()
393 * You can lose return values below, but we report all errors, and it's in brcmstb_gpio_remove()
396 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_remove()
397 gpiochip_remove(&bank->gc); in brcmstb_gpio_remove()
409 if (gc->of_gpio_n_cells != 2) { in brcmstb_gpio_of_xlate()
411 return -EINVAL; in brcmstb_gpio_of_xlate()
414 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) in brcmstb_gpio_of_xlate()
415 return -EINVAL; in brcmstb_gpio_of_xlate()
417 offset = gpiospec->args[0] - (gc->base - priv->gpio_base); in brcmstb_gpio_of_xlate()
418 if (offset >= gc->ngpio || offset < 0) in brcmstb_gpio_of_xlate()
419 return -EINVAL; in brcmstb_gpio_of_xlate()
421 if (unlikely(offset >= bank->width)) { in brcmstb_gpio_of_xlate()
422 dev_warn_ratelimited(&priv->pdev->dev, in brcmstb_gpio_of_xlate()
424 gpiospec->args[0]); in brcmstb_gpio_of_xlate()
428 *flags = gpiospec->args[1]; in brcmstb_gpio_of_xlate()
433 /* priv->parent_irq and priv->num_gpios must be set before calling */
437 struct device *dev = &pdev->dev; in brcmstb_gpio_irq_setup()
438 struct device_node *np = dev->of_node; in brcmstb_gpio_irq_setup()
441 priv->irq_domain = in brcmstb_gpio_irq_setup()
442 irq_domain_add_linear(np, priv->num_gpios, in brcmstb_gpio_irq_setup()
445 if (!priv->irq_domain) { in brcmstb_gpio_irq_setup()
446 dev_err(dev, "Couldn't allocate IRQ domain\n"); in brcmstb_gpio_irq_setup()
447 return -ENXIO; in brcmstb_gpio_irq_setup()
450 if (of_property_read_bool(np, "wakeup-source")) { in brcmstb_gpio_irq_setup()
451 priv->parent_wake_irq = platform_get_irq(pdev, 1); in brcmstb_gpio_irq_setup()
452 if (priv->parent_wake_irq < 0) { in brcmstb_gpio_irq_setup()
453 priv->parent_wake_irq = 0; in brcmstb_gpio_irq_setup()
455 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); in brcmstb_gpio_irq_setup()
458 * Set wakeup capability so we can process boot-time in brcmstb_gpio_irq_setup()
463 err = devm_request_irq(dev, priv->parent_wake_irq, in brcmstb_gpio_irq_setup()
466 "brcmstb-gpio-wake", priv); in brcmstb_gpio_irq_setup()
469 dev_err(dev, "Couldn't request wake IRQ"); in brcmstb_gpio_irq_setup()
475 priv->irq_chip.name = dev_name(dev); in brcmstb_gpio_irq_setup()
476 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask; in brcmstb_gpio_irq_setup()
477 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask; in brcmstb_gpio_irq_setup()
478 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; in brcmstb_gpio_irq_setup()
479 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack; in brcmstb_gpio_irq_setup()
480 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; in brcmstb_gpio_irq_setup()
482 if (priv->parent_wake_irq) in brcmstb_gpio_irq_setup()
483 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; in brcmstb_gpio_irq_setup()
485 irq_set_chained_handler_and_data(priv->parent_irq, in brcmstb_gpio_irq_setup()
487 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); in brcmstb_gpio_irq_setup()
492 irq_domain_remove(priv->irq_domain); in brcmstb_gpio_irq_setup()
500 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_save()
504 bank->saved_regs[i] = gc->read_reg(priv->reg_base + in brcmstb_gpio_bank_save()
505 GIO_BANK_OFF(bank->id, i)); in brcmstb_gpio_bank_save()
515 /* disable non-wake interrupt */ in brcmstb_gpio_quiesce()
516 if (priv->parent_irq >= 0) in brcmstb_gpio_quiesce()
517 disable_irq(priv->parent_irq); in brcmstb_gpio_quiesce()
519 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_quiesce()
520 gc = &bank->gc; in brcmstb_gpio_quiesce()
525 /* Unmask GPIOs which have been flagged as wake-up sources */ in brcmstb_gpio_quiesce()
526 if (priv->parent_wake_irq) in brcmstb_gpio_quiesce()
527 imask = bank->wake_active; in brcmstb_gpio_quiesce()
530 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), in brcmstb_gpio_quiesce()
538 brcmstb_gpio_quiesce(&pdev->dev, false); in brcmstb_gpio_shutdown()
545 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_restore()
549 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), in brcmstb_gpio_bank_restore()
550 bank->saved_regs[i]); in brcmstb_gpio_bank_restore()
565 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_resume()
570 if (priv->parent_wake_irq && need_wakeup_event) in brcmstb_gpio_resume()
573 /* enable non-wake interrupt */ in brcmstb_gpio_resume()
574 if (priv->parent_irq >= 0) in brcmstb_gpio_resume()
575 enable_irq(priv->parent_irq); in brcmstb_gpio_resume()
592 struct device *dev = &pdev->dev; in brcmstb_gpio_probe()
593 struct device_node *np = dev->of_node; in brcmstb_gpio_probe()
608 return -ENOMEM; in brcmstb_gpio_probe()
610 INIT_LIST_HEAD(&priv->bank_list); in brcmstb_gpio_probe()
616 priv->gpio_base = gpio_base; in brcmstb_gpio_probe()
617 priv->reg_base = reg_base; in brcmstb_gpio_probe()
618 priv->pdev = pdev; in brcmstb_gpio_probe()
620 if (of_property_read_bool(np, "interrupt-controller")) { in brcmstb_gpio_probe()
621 priv->parent_irq = platform_get_irq(pdev, 0); in brcmstb_gpio_probe()
622 if (priv->parent_irq <= 0) in brcmstb_gpio_probe()
623 return -ENOENT; in brcmstb_gpio_probe()
625 priv->parent_irq = -ENOENT; in brcmstb_gpio_probe()
629 return -EINVAL; in brcmstb_gpio_probe()
633 * bus endianness (i.e., big-endian CPU + big endian bus ==> native in brcmstb_gpio_probe()
643 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, in brcmstb_gpio_probe()
662 err = -ENOMEM; in brcmstb_gpio_probe()
666 bank->parent_priv = priv; in brcmstb_gpio_probe()
667 bank->id = num_banks; in brcmstb_gpio_probe()
670 err = -EINVAL; in brcmstb_gpio_probe()
673 bank->width = bank_width; in brcmstb_gpio_probe()
680 gc = &bank->gc; in brcmstb_gpio_probe()
682 reg_base + GIO_DATA(bank->id), in brcmstb_gpio_probe()
684 reg_base + GIO_IODIR(bank->id), flags); in brcmstb_gpio_probe()
690 gc->owner = THIS_MODULE; in brcmstb_gpio_probe()
691 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); in brcmstb_gpio_probe()
692 if (!gc->label) { in brcmstb_gpio_probe()
693 err = -ENOMEM; in brcmstb_gpio_probe()
696 gc->base = gpio_base; in brcmstb_gpio_probe()
697 gc->of_gpio_n_cells = 2; in brcmstb_gpio_probe()
698 gc->of_xlate = brcmstb_gpio_of_xlate; in brcmstb_gpio_probe()
700 gc->ngpio = MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
701 gc->offset = bank->id * MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
702 if (priv->parent_irq > 0) in brcmstb_gpio_probe()
703 gc->to_irq = brcmstb_gpio_to_irq; in brcmstb_gpio_probe()
710 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
715 bank->id); in brcmstb_gpio_probe()
718 gpio_base += gc->ngpio; in brcmstb_gpio_probe()
720 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, in brcmstb_gpio_probe()
721 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()
724 list_add(&bank->node, &priv->bank_list); in brcmstb_gpio_probe()
729 priv->num_gpios = gpio_base - priv->gpio_base; in brcmstb_gpio_probe()
730 if (priv->parent_irq > 0) { in brcmstb_gpio_probe()
736 if (priv->parent_wake_irq && need_wakeup_event) in brcmstb_gpio_probe()
747 { .compatible = "brcm,brcmstb-gpio" },
755 .name = "brcmstb-gpio",