Lines Matching refs:GENMASK_ULL
71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77 #define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
78 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
99 #define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
102 #define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
103 #define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
105 #define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
108 #define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
109 #define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */
110 #define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */
115 #define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)
116 #define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)
119 #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
133 #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
139 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
140 #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
141 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
142 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
146 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
148 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
160 #define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
176 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
177 #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
178 #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
189 #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
200 #define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
206 #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
207 #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */