62 	} tx;  member
102 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_empty()  local
115 	if (tx - rx > ivc->num_frames)  in tegra_ivc_empty()
118 	return tx == rx;  in tegra_ivc_empty()
123 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_full()  local
130 	return tx - rx >= ivc->num_frames;  in tegra_ivc_full()
135 	u32 tx = tegra_ivc_header_read_field(map, tx.count);  in tegra_ivc_available()  local
144 	return tx - rx;  in tegra_ivc_available()
149 	unsigned int count = tegra_ivc_header_read_field(&ivc->tx.map, tx.count);  in tegra_ivc_advance_tx()
151 	tegra_ivc_header_write_field(&ivc->tx.map, tx.count, count + 1);  in tegra_ivc_advance_tx()
153 	if (ivc->tx.position == ivc->num_frames - 1)  in tegra_ivc_advance_tx()
154 		ivc->tx.position = 0;  in tegra_ivc_advance_tx()
156 		ivc->tx.position++;  in tegra_ivc_advance_tx()
173 	unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_check_read()
184 	state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_check_read()
211 	state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_check_write()
215 	if (!tegra_ivc_full(ivc, &ivc->tx.map))  in tegra_ivc_check_write()
218 	tegra_ivc_invalidate(ivc, ivc->tx.phys + offset);  in tegra_ivc_check_write()
220 	if (tegra_ivc_full(ivc, &ivc->tx.map))  in tegra_ivc_check_write()
306 	unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_read_advance()  local
333 	tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);  in tegra_ivc_read_advance()
351 	return tegra_ivc_frame_virt(ivc, &ivc->tx.map, ivc->tx.position, map);  in tegra_ivc_write_get_next_frame()
358 	unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_write_advance()  local
366 	tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0,  in tegra_ivc_write_advance()
376 	tegra_ivc_flush(ivc, ivc->tx.phys + tx);  in tegra_ivc_write_advance()
389 	tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);  in tegra_ivc_write_advance()
391 	if (tegra_ivc_available(ivc, &ivc->tx.map) == 1)  in tegra_ivc_write_advance()
400 	unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_reset()
402 	tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_SYNC);  in tegra_ivc_reset()
403 	tegra_ivc_flush(ivc, ivc->tx.phys + offset);  in tegra_ivc_reset()
430 	unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_notified()
435 	rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state);  in tegra_ivc_notified()
436 	tx_state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);  in tegra_ivc_notified()
439 		offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_notified()
452 		tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);  in tegra_ivc_notified()
455 		ivc->tx.position = 0;  in tegra_ivc_notified()
468 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ACK);  in tegra_ivc_notified()
469 		tegra_ivc_flush(ivc, ivc->tx.phys + offset);  in tegra_ivc_notified()
478 		offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_notified()
491 		tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);  in tegra_ivc_notified()
494 		ivc->tx.position = 0;  in tegra_ivc_notified()
508 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);  in tegra_ivc_notified()
509 		tegra_ivc_flush(ivc, ivc->tx.phys + offset);  in tegra_ivc_notified()
517 		offset = offsetof(struct tegra_ivc_header, tx.count);  in tegra_ivc_notified()
532 		tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);  in tegra_ivc_notified()
533 		tegra_ivc_flush(ivc, ivc->tx.phys + offset);  in tegra_ivc_notified()
574 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,  in tegra_ivc_check_params()  argument
577 	BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count),  in tegra_ivc_check_params()
603 	if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) {  in tegra_ivc_check_params()
604 		pr_err("IVC channel start not aligned: %#lx\n", tx);  in tegra_ivc_check_params()
608 	if (rx < tx) {  in tegra_ivc_check_params()
609 		if (rx + frame_size * num_frames > tx) {  in tegra_ivc_check_params()
611 			       rx, frame_size * num_frames, tx);  in tegra_ivc_check_params()
615 		if (tx + frame_size * num_frames > rx) {  in tegra_ivc_check_params()
617 			       tx, frame_size * num_frames, rx);  in tegra_ivc_check_params()
647 		   dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys,  in tegra_ivc_init()  argument
665 	err = tegra_ivc_check_params(iosys_map_get_address(rx), iosys_map_get_address(tx),  in tegra_ivc_init()
678 		ivc->tx.phys = dma_map_single(peer, iosys_map_get_vaddr(tx), queue_size,  in tegra_ivc_init()
680 		if (dma_mapping_error(peer, ivc->tx.phys)) {  in tegra_ivc_init()
687 		ivc->tx.phys = tx_phys;  in tegra_ivc_init()
691 	iosys_map_copy(&ivc->tx.map, tx);  in tegra_ivc_init()
702 	ivc->tx.position = 0;  in tegra_ivc_init()
717 		dma_unmap_single(ivc->peer, ivc->tx.phys, size,  in tegra_ivc_cleanup()