1116 static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)  in umc_normaddr_to_sysaddr()  argument
1136 	ctx.inst_id = umc;  in umc_normaddr_to_sysaddr()
1139 	if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1153 	if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1176 	if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1232 		if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))  in umc_normaddr_to_sysaddr()
1348 		if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))  in umc_determine_edac_cap()
1354 		if (pvt->umc[i].umc_cfg & BIT(12))  in umc_determine_edac_cap()
1533 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in umc_addr_mask_to_cs_size()  argument
1577 		addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];  in umc_addr_mask_to_cs_size()
1579 		addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];  in umc_addr_mask_to_cs_size()
1607 	struct amd64_umc *umc;  in umc_dump_misc_regs()  local
1612 		umc = &pvt->umc[i];  in umc_dump_misc_regs()
1614 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in umc_dump_misc_regs()
1615 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in umc_dump_misc_regs()
1616 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in umc_dump_misc_regs()
1617 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in umc_dump_misc_regs()
1624 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in umc_dump_misc_regs()
1627 				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",  in umc_dump_misc_regs()
1628 				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");  in umc_dump_misc_regs()
1630 				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");  in umc_dump_misc_regs()
1632 				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");  in umc_dump_misc_regs()
1634 				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");  in umc_dump_misc_regs()
1636 		if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {  in umc_dump_misc_regs()
1704 	int umc;  in umc_prep_chip_selects()  local
1706 	for_each_umc(umc) {  in umc_prep_chip_selects()
1707 		pvt->csels[umc].b_cnt = 4;  in umc_prep_chip_selects()
1708 		pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2;  in umc_prep_chip_selects()
1720 	int cs, umc;  in umc_read_base_mask()  local
1722 	for_each_umc(umc) {  in umc_read_base_mask()
1723 		umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;  in umc_read_base_mask()
1724 		umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;  in umc_read_base_mask()
1726 		for_each_chip_select(cs, umc, pvt) {  in umc_read_base_mask()
1727 			base = &pvt->csels[umc].csbases[cs];  in umc_read_base_mask()
1728 			base_sec = &pvt->csels[umc].csbases_sec[cs];  in umc_read_base_mask()
1735 					 umc, cs, *base, base_reg);  in umc_read_base_mask()
1739 					 umc, cs, *base_sec, base_reg_sec);  in umc_read_base_mask()
1742 		umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;  in umc_read_base_mask()
1743 		umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(pvt, UMCCH_ADDR_MASK_SEC);  in umc_read_base_mask()
1745 		for_each_chip_select_mask(cs, umc, pvt) {  in umc_read_base_mask()
1746 			mask = &pvt->csels[umc].csmasks[cs];  in umc_read_base_mask()
1747 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];  in umc_read_base_mask()
1754 					 umc, cs, *mask, mask_reg);  in umc_read_base_mask()
1758 					 umc, cs, *mask_sec, mask_reg_sec);  in umc_read_base_mask()
1811 	struct amd64_umc *umc;  in umc_determine_memory_type()  local
1815 		umc = &pvt->umc[i];  in umc_determine_memory_type()
1817 		if (!(umc->sdp_ctrl & UMC_SDP_INIT)) {  in umc_determine_memory_type()
1818 			umc->dram_type = MEM_EMPTY;  in umc_determine_memory_type()
1826 		if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {  in umc_determine_memory_type()
1827 			if (umc->dimm_cfg & BIT(5))  in umc_determine_memory_type()
1828 				umc->dram_type = MEM_LRDDR5;  in umc_determine_memory_type()
1829 			else if (umc->dimm_cfg & BIT(4))  in umc_determine_memory_type()
1830 				umc->dram_type = MEM_RDDR5;  in umc_determine_memory_type()
1832 				umc->dram_type = MEM_DDR5;  in umc_determine_memory_type()
1834 			if (umc->dimm_cfg & BIT(5))  in umc_determine_memory_type()
1835 				umc->dram_type = MEM_LRDDR4;  in umc_determine_memory_type()
1836 			else if (umc->dimm_cfg & BIT(4))  in umc_determine_memory_type()
1837 				umc->dram_type = MEM_RDDR4;  in umc_determine_memory_type()
1839 				umc->dram_type = MEM_DDR4;  in umc_determine_memory_type()
1842 		edac_dbg(1, "  UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);  in umc_determine_memory_type()
3170 	struct amd64_umc *umc;  in umc_read_mc_regs()  local
3177 		umc = &pvt->umc[i];  in umc_read_mc_regs()
3179 		amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &umc->dimm_cfg);  in umc_read_mc_regs()
3180 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in umc_read_mc_regs()
3181 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in umc_read_mc_regs()
3182 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in umc_read_mc_regs()
3183 		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);  in umc_read_mc_regs()
3330 	u8 umc, cs;  in umc_init_csrows()  local
3345 	for_each_umc(umc) {  in umc_init_csrows()
3346 		for_each_chip_select(cs, umc, pvt) {  in umc_init_csrows()
3347 			if (!csrow_enabled(cs, umc, pvt))  in umc_init_csrows()
3350 			dimm = mci->csrows[cs]->channels[umc]->dimm;  in umc_init_csrows()
3355 			dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs);  in umc_init_csrows()
3356 			dimm->mtype = pvt->umc[umc].dram_type;  in umc_init_csrows()
3623 	struct amd64_umc *umc;  in umc_ecc_enabled()  local
3627 		umc = &pvt->umc[i];  in umc_ecc_enabled()
3630 		if (!(umc->sdp_ctrl & UMC_SDP_INIT))  in umc_ecc_enabled()
3635 		if (umc->umc_cap_hi & UMC_ECC_ENABLED)  in umc_ecc_enabled()
3659 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in umc_determine_edac_ctl_cap()
3660 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);  in umc_determine_edac_ctl_cap()
3661 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);  in umc_determine_edac_ctl_cap()
3663 			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));  in umc_determine_edac_ctl_cap()
3664 			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));  in umc_determine_edac_ctl_cap()
3745 	pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);  in umc_hw_info_get()
3746 	if (!pvt->umc)  in umc_hw_info_get()
3783 static int gpu_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in gpu_addr_mask_to_cs_size()  argument
3786 	u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr];  in gpu_addr_mask_to_cs_size()
3807 	struct amd64_umc *umc;  in gpu_dump_misc_regs()  local
3811 		umc = &pvt->umc[i];  in gpu_dump_misc_regs()
3813 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in gpu_dump_misc_regs()
3814 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in gpu_dump_misc_regs()
3815 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in gpu_dump_misc_regs()
3840 	u8 umc, cs;  in gpu_init_csrows()  local
3842 	for_each_umc(umc) {  in gpu_init_csrows()
3843 		for_each_chip_select(cs, umc, pvt) {  in gpu_init_csrows()
3844 			if (!csrow_enabled(cs, umc, pvt))  in gpu_init_csrows()
3847 			dimm = mci->csrows[umc]->channels[cs]->dimm;  in gpu_init_csrows()
3852 			dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs);  in gpu_init_csrows()
3883 static inline u32 gpu_get_umc_base(u8 umc, u8 channel)  in gpu_get_umc_base()  argument
3897 	umc *= 2;  in gpu_get_umc_base()
3900 		umc++;  in gpu_get_umc_base()
3902 	return 0x50000 + (umc << 20) + ((channel % 4) << 12);  in gpu_get_umc_base()
3908 	struct amd64_umc *umc;  in gpu_read_mc_regs()  local
3914 		umc = &pvt->umc[i];  in gpu_read_mc_regs()
3916 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in gpu_read_mc_regs()
3917 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in gpu_read_mc_regs()
3918 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in gpu_read_mc_regs()
3926 	int umc, cs;  in gpu_read_base_mask()  local
3928 	for_each_umc(umc) {  in gpu_read_base_mask()
3929 		for_each_chip_select(cs, umc, pvt) {  in gpu_read_base_mask()
3930 			base_reg = gpu_get_umc_base(umc, cs) + UMCCH_BASE_ADDR;  in gpu_read_base_mask()
3931 			base = &pvt->csels[umc].csbases[cs];  in gpu_read_base_mask()
3935 					 umc, cs, *base, base_reg);  in gpu_read_base_mask()
3938 			mask_reg = gpu_get_umc_base(umc, cs) + UMCCH_ADDR_MASK;  in gpu_read_base_mask()
3939 			mask = &pvt->csels[umc].csmasks[cs];  in gpu_read_base_mask()
3943 					 umc, cs, *mask, mask_reg);  in gpu_read_base_mask()
3951 	int umc;  in gpu_prep_chip_selects()  local
3953 	for_each_umc(umc) {  in gpu_prep_chip_selects()
3954 		pvt->csels[umc].b_cnt = 8;  in gpu_prep_chip_selects()
3955 		pvt->csels[umc].m_cnt = 8;  in gpu_prep_chip_selects()
3967 	pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);  in gpu_hw_info_get()
3968 	if (!pvt->umc)  in gpu_hw_info_get()
3982 	kfree(pvt->umc);  in hw_info_put()