1468 	int cs_mode = 0;  in umc_get_cs_mode()  local
1471 		cs_mode |= CS_EVEN_PRIMARY;  in umc_get_cs_mode()
1474 		cs_mode |= CS_ODD_PRIMARY;  in umc_get_cs_mode()
1478 		cs_mode |= CS_ODD_SECONDARY;  in umc_get_cs_mode()
1491 		cs_mode |= CS_3R_INTERLEAVE;  in umc_get_cs_mode()
1494 	return cs_mode;  in umc_get_cs_mode()
1497 static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode,  in __addr_mask_to_cs_size()  argument
1517 	num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);  in __addr_mask_to_cs_size()
1534 				    unsigned int cs_mode, int csrow_nr)  in umc_addr_mask_to_cs_size()  argument
1541 	if (!cs_mode)  in umc_addr_mask_to_cs_size()
1545 	if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))  in umc_addr_mask_to_cs_size()
1549 	if (!(cs_mode & CS_ODD) && (csrow_nr & 1))  in umc_addr_mask_to_cs_size()
1576 	if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))  in umc_addr_mask_to_cs_size()
1581 	return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);  in umc_addr_mask_to_cs_size()
1586 	int dimm, size0, size1, cs0, cs1, cs_mode;  in umc_debug_display_dimm_sizes()  local
1594 		cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);  in umc_debug_display_dimm_sizes()
1596 		size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);  in umc_debug_display_dimm_sizes()
1597 		size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);  in umc_debug_display_dimm_sizes()
2112 				  unsigned cs_mode, int cs_mask_nr)  in k8_dbam_to_chip_select()  argument
2117 		WARN_ON(cs_mode > 11);  in k8_dbam_to_chip_select()
2118 		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);  in k8_dbam_to_chip_select()
2122 		WARN_ON(cs_mode > 10);  in k8_dbam_to_chip_select()
2148 		diff = cs_mode/3 + (unsigned)(cs_mode > 5);  in k8_dbam_to_chip_select()
2150 		return 32 << (cs_mode - diff);  in k8_dbam_to_chip_select()
2153 		WARN_ON(cs_mode > 6);  in k8_dbam_to_chip_select()
2154 		return 32 << cs_mode;  in k8_dbam_to_chip_select()
2216 				   unsigned cs_mode, int cs_mask_nr)  in f10_dbam_to_chip_select()  argument
2220 	WARN_ON(cs_mode > 11);  in f10_dbam_to_chip_select()
2223 		return ddr3_cs_size(cs_mode, dclr & WIDTH_128);  in f10_dbam_to_chip_select()
2225 		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);  in f10_dbam_to_chip_select()
2232 				   unsigned cs_mode, int cs_mask_nr)  in f15_dbam_to_chip_select()  argument
2234 	WARN_ON(cs_mode > 12);  in f15_dbam_to_chip_select()
2236 	return ddr3_cs_size(cs_mode, false);  in f15_dbam_to_chip_select()
2241 					unsigned cs_mode, int cs_mask_nr)  in f15_m60h_dbam_to_chip_select()  argument
2246 	WARN_ON(cs_mode > 12);  in f15_m60h_dbam_to_chip_select()
2249 		if (cs_mode > 9)  in f15_m60h_dbam_to_chip_select()
2252 		cs_size = ddr4_cs_size(cs_mode);  in f15_m60h_dbam_to_chip_select()
2258 		cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);  in f15_m60h_dbam_to_chip_select()
2261 		if (cs_mode == 0x1)  in f15_m60h_dbam_to_chip_select()
2264 		cs_size = ddr3_cs_size(cs_mode, false);  in f15_m60h_dbam_to_chip_select()
2274 				unsigned cs_mode, int cs_mask_nr)  in f16_dbam_to_chip_select()  argument
2276 	WARN_ON(cs_mode > 12);  in f16_dbam_to_chip_select()
2278 	if (cs_mode == 6 || cs_mode == 8 ||  in f16_dbam_to_chip_select()
2279 	    cs_mode == 9 || cs_mode == 12)  in f16_dbam_to_chip_select()
2282 		return ddr3_cs_size(cs_mode, false);  in f16_dbam_to_chip_select()
3292 	u32 cs_mode, nr_pages;  in dct_get_csrow_nr_pages()  local
3295 	cs_mode = DBAM_DIMM(csrow_nr, dbam);  in dct_get_csrow_nr_pages()
3297 	nr_pages   = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);  in dct_get_csrow_nr_pages()
3301 		    csrow_nr, dct,  cs_mode);  in dct_get_csrow_nr_pages()
3310 	u32 cs_mode, nr_pages;  in umc_get_csrow_nr_pages()  local
3312 	cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);  in umc_get_csrow_nr_pages()
3314 	nr_pages   = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);  in umc_get_csrow_nr_pages()
3318 		 csrow_nr_orig, dct,  cs_mode);  in umc_get_csrow_nr_pages()
3784 				    unsigned int cs_mode, int csrow_nr)  in gpu_addr_mask_to_cs_size()  argument
3788 	return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1);  in gpu_addr_mask_to_cs_size()
3793 	int size, cs_mode, cs = 0;  in gpu_debug_display_dimm_sizes()  local
3797 	cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;  in gpu_debug_display_dimm_sizes()
3800 		size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs);  in gpu_debug_display_dimm_sizes()
3825 	int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;  in gpu_get_csrow_nr_pages()  local
3827 	nr_pages   = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);  in gpu_get_csrow_nr_pages()