Lines Matching +full:error +full:- +full:correction
13 tristate "EDAC (Error Detection And Correction) reporting"
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
82 Support for error detection and correction of DRAM ECC errors on
85 When EDAC_DEBUG is enabled, hardware error injection facilities
89 Error Injection into the ECC detection circuits. The amd64_edac
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
114 Support for error detection and correction on the AMD 76x
121 Support for error detection and correction on the Intel
128 Support for error detection and correction on the Intel
136 Support for error detection and correction on the Intel
143 Support for error detection and correction on the Intel
150 Support for error detection and correction on the Intel
157 Support for error detection and correction on the Intel
164 Support for error detection and correction on the Intel
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
178 Support for error detection and correction on the Intel
185 Support for error detection and correction the Intel
192 Support for error detection and correction the Intel
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Radisys
216 Support for error detection and correction the Intel
223 Support for error detection and correction the Intel
230 Support for error detection and correction the Intel
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
237 Support for error detection and correction the Intel
247 Support for error detection and correction the Intel
249 system has non-volatile DIMMs you should also manually
259 Support for error detection and correction the Intel
261 system has non-volatile DIMMs you should also manually
269 Support for error detection and correction on the Intel
272 micro-server but may appear on others in the future.
279 Support for error detection and correction on the Intel
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
288 Support for error detection and correction on the Freescale
295 Support for error detection and correction on Freescale memory
302 Support for error detection and correction on PA Semi
309 Support for error detection and correction on the
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
326 Support for error detection and correction on the
327 AMD8131 HyperTransport PCI-X Tunnel chip.
335 Support for error detection and correction on the
344 Support for error detection and correction on the
353 Support for error detection and correction on the
360 Support for error detection and correction on the
367 Support for error detection and correction on the primary caches of
374 Support for error detection and correction on the
381 Support for error detection and correction on the
388 Support for error detection and correction on the
396 Support for error detection and correction on the
405 Support for error detection and correction on the
413 Support for error detection and correction on the
422 Support for error detection and correction on the
427 bool "Altera On-Chip RAM ECC"
430 Support for error detection and correction on the
431 Altera On-Chip RAM Memory for Altera SoCs.
437 Support for error detection and correction on the
444 Support for error detection and correction on the
451 Support for error detection and correction on the
458 Support for error detection and correction on the
465 Support for error detection and correction on the
472 Support for error detection and correction on the
479 Support for error detection and correction on the SiFive SoCs.
485 Support for error correction and detection on the Marvell Aramada XP
492 Support for error detection and correction on the Synopsys DDR
496 tristate "APM X-Gene SoC"
499 Support for error detection and correction on the
500 APM X-Gene family of SOCs.
506 Support for error detection and correction on the TI SoCs.
512 Support for error detection and correction on the
516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
526 Support for error detection and correction on the Aspeed AST BMC SoC.
529 will expose error counters via the EDAC kernel framework.
535 Support for error detection and correction on the
539 tristate "ARM DMC-520 ECC"
542 Support for error detection and correction on the
543 SoCs with ARM DMC-520 DRAM controller.
549 This driver supports error detection and correction for the
557 Support for error detection and correction on the Nuvoton NPCM DDR
560 The memory controller supports single bit error correction, double bit
561 error detection (in-line ECC in which a section 1/8th of the memory