Lines Matching refs:TXX9_DMA_REG32
60 #define TXX9_DMA_REG32(name) u32 __pad_##name; u32 name macro
62 #define TXX9_DMA_REG32(name) u32 name; u32 __pad_##name macro
68 TXX9_DMA_REG32(CHAR); /* Chain Address Register */
74 TXX9_DMA_REG32(CNTR); /* Count Register */
75 TXX9_DMA_REG32(SAIR); /* Source Address Increment Register */
76 TXX9_DMA_REG32(DAIR); /* Destination Address Increment Register */
77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
78 TXX9_DMA_REG32(CSR); /* Channel Status Register */
96 TXX9_DMA_REG32(MCR); /* Master Control Register */
202 TXX9_DMA_REG32(CHAR);
208 TXX9_DMA_REG32(CNTR);