Lines Matching refs:edma_shadow0_write_array
370 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() function
409 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_setup_interrupt()
410 edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit); in edma_setup_interrupt()
412 edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit); in edma_setup_interrupt()
557 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_start()
566 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_start()
567 edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit); in edma_start()
580 edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit); in edma_stop()
581 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_stop()
582 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_stop()
586 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit); in edma_stop()
604 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
614 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
626 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit); in edma_trigger_channel()
641 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit); in edma_clean_channel()
645 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit); in edma_clean_channel()
1527 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1633 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()