Lines Matching +full:tegra194 +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
203 * sub-transfer as per requester details and hw support. This sub transfer
263 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
268 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_read()
271 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc) in to_tegra_dma_chan() argument
273 return container_of(dc, struct tegra_dma_channel, vc.chan); in to_tegra_dma_chan()
283 return tdc->vc.chan.device->dev; in tdc2dev()
289 tdc->id, tdc->name); in tegra_dma_dump_chan_regs()
311 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_reserve()
312 int sid = tdc->slave_id; in tegra_dma_sid_reserve()
319 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) { in tegra_dma_sid_reserve()
320 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
321 return -EINVAL; in tegra_dma_sid_reserve()
325 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) { in tegra_dma_sid_reserve()
326 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
327 return -EINVAL; in tegra_dma_sid_reserve()
334 tdc->sid_dir = direction; in tegra_dma_sid_reserve()
341 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_free()
342 int sid = tdc->slave_id; in tegra_dma_sid_free()
344 switch (tdc->sid_dir) { in tegra_dma_sid_free()
346 clear_bit(sid, &tdma->sid_m2d_reserved); in tegra_dma_sid_free()
349 clear_bit(sid, &tdma->sid_d2m_reserved); in tegra_dma_sid_free()
355 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_sid_free()
363 static int tegra_dma_slave_config(struct dma_chan *dc, in tegra_dma_slave_config() argument
366 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config()
368 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
369 tdc->config_init = true; in tegra_dma_slave_config()
383 /* Wait until busy bit is de-asserted */ in tegra_dma_pause()
384 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_pause()
385 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_pause()
399 static int tegra_dma_device_pause(struct dma_chan *dc) in tegra_dma_device_pause() argument
401 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_pause()
405 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_pause()
406 return -ENOSYS; in tegra_dma_device_pause()
408 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_pause()
410 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_pause()
424 static int tegra_dma_device_resume(struct dma_chan *dc) in tegra_dma_device_resume() argument
426 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_resume()
429 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_resume()
430 return -ENOSYS; in tegra_dma_device_resume()
432 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_resume()
434 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_resume()
473 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_configure_next_sg()
478 dma_desc->sg_idx++; in tegra_dma_configure_next_sg()
481 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_configure_next_sg()
482 dma_desc->sg_idx = 0; in tegra_dma_configure_next_sg()
485 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_configure_next_sg()
486 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_configure_next_sg()
493 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_configure_next_sg()
495 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_configure_next_sg()
496 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_configure_next_sg()
497 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_configure_next_sg()
498 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_configure_next_sg()
502 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_configure_next_sg()
507 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_start()
512 vdesc = vchan_next_desc(&tdc->vc); in tegra_dma_start()
517 list_del(&vdesc->node); in tegra_dma_start()
518 dma_desc->tdc = tdc; in tegra_dma_start()
519 tdc->dma_desc = dma_desc; in tegra_dma_start()
524 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_start()
526 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
528 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_start()
529 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_start()
530 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_start()
531 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); in tegra_dma_start()
532 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); in tegra_dma_start()
533 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); in tegra_dma_start()
534 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
538 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_start()
543 vchan_cookie_complete(&tdc->dma_desc->vd); in tegra_dma_xfer_complete()
546 tdc->dma_desc = NULL; in tegra_dma_xfer_complete()
554 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
555 "GPCDMA CH%d bm fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
559 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
560 "GPCDMA CH%d peripheral fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
564 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
565 "GPCDMA CH%d illegal peripheral id\n", tdc->id); in tegra_dma_chan_decode_error()
569 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
570 "GPCDMA CH%d illegal stream id\n", tdc->id); in tegra_dma_chan_decode_error()
574 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
575 "GPCDMA CH%d mc slave error\n", tdc->id); in tegra_dma_chan_decode_error()
579 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
580 "GPCDMA CH%d mmio slave error\n", tdc->id); in tegra_dma_chan_decode_error()
584 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
585 "GPCDMA CH%d security violation %x\n", tdc->id, in tegra_dma_chan_decode_error()
593 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_isr()
605 spin_lock(&tdc->vc.lock); in tegra_dma_isr()
616 sg_req = dma_desc->sg_req; in tegra_dma_isr()
617 dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len; in tegra_dma_isr()
619 if (dma_desc->cyclic) { in tegra_dma_isr()
620 vchan_cyclic_callback(&dma_desc->vd); in tegra_dma_isr()
623 dma_desc->sg_idx++; in tegra_dma_isr()
624 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_isr()
631 spin_unlock(&tdc->vc.lock); in tegra_dma_isr()
635 static void tegra_dma_issue_pending(struct dma_chan *dc) in tegra_dma_issue_pending() argument
637 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending()
640 if (tdc->dma_desc) in tegra_dma_issue_pending()
643 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
644 if (vchan_issue_pending(&tdc->vc)) in tegra_dma_issue_pending()
654 if (tdc->dma_desc && tdc->dma_desc->cyclic) in tegra_dma_issue_pending()
657 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
682 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_stop_client()
683 tdc->chan_base_offset + in tegra_dma_stop_client()
698 static int tegra_dma_terminate_all(struct dma_chan *dc) in tegra_dma_terminate_all() argument
700 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all()
705 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
707 if (tdc->dma_desc) { in tegra_dma_terminate_all()
708 err = tdc->tdma->chip_data->terminate(tdc); in tegra_dma_terminate_all()
710 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
714 vchan_terminate_vdesc(&tdc->dma_desc->vd); in tegra_dma_terminate_all()
716 tdc->dma_desc = NULL; in tegra_dma_terminate_all()
720 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_dma_terminate_all()
721 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
723 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_dma_terminate_all()
730 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_get_residual()
731 struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; in tegra_dma_get_residual()
746 bytes_xfer = dma_desc->bytes_xfer + in tegra_dma_get_residual()
747 sg_req[dma_desc->sg_idx].len - (wcount * 4); in tegra_dma_get_residual()
749 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); in tegra_dma_get_residual()
754 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, in tegra_dma_tx_status() argument
758 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status()
765 ret = dma_cookie_status(dc, cookie, txstate); in tegra_dma_tx_status()
769 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_tx_status()
770 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_dma_tx_status()
773 residual = dma_desc->bytes_req; in tegra_dma_tx_status()
775 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { in tegra_dma_tx_status()
781 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_tx_status()
798 return -EINVAL; in get_bus_width()
835 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
836 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
837 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
838 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
842 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
843 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
844 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
845 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
852 return -EINVAL; in get_transfer_param()
856 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value, in tegra_dma_prep_dma_memset() argument
859 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memset()
860 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memset()
884 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memset()
902 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memset()
903 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memset()
904 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memset()
912 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memset()
918 dma_desc->cyclic = false; in tegra_dma_prep_dma_memset()
919 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memset()
923 tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest, in tegra_dma_prep_dma_memcpy() argument
926 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memcpy()
932 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memcpy()
952 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memcpy()
971 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memcpy()
972 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memcpy()
973 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memcpy()
982 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memcpy()
988 dma_desc->cyclic = false; in tegra_dma_prep_dma_memcpy()
989 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memcpy()
993 tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl, in tegra_dma_prep_slave_sg() argument
997 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg()
998 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_slave_sg()
1008 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1029 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_slave_sg()
1040 /* retain stream-id and clean rest */ in tegra_dma_prep_slave_sg()
1064 dma_desc->sg_count = sg_len; in tegra_dma_prep_slave_sg()
1065 sg_req = dma_desc->sg_req; in tegra_dma_prep_slave_sg()
1083 dma_desc->bytes_req += len; in tegra_dma_prep_slave_sg()
1101 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_slave_sg()
1108 dma_desc->cyclic = false; in tegra_dma_prep_slave_sg()
1109 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_slave_sg()
1113 tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, in tegra_dma_prep_dma_cyclic() argument
1120 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic()
1131 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1150 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_cyclic()
1164 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_dma_cyclic()
1177 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_cyclic()
1200 dma_desc->bytes_req = buf_len; in tegra_dma_prep_dma_cyclic()
1201 dma_desc->sg_count = period_count; in tegra_dma_prep_dma_cyclic()
1202 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_cyclic()
1222 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_cyclic()
1231 dma_desc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1233 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_cyclic()
1236 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc) in tegra_dma_alloc_chan_resources() argument
1238 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources()
1241 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_alloc_chan_resources()
1243 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); in tegra_dma_alloc_chan_resources()
1247 dma_cookie_init(&tdc->vc.chan); in tegra_dma_alloc_chan_resources()
1248 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1252 static void tegra_dma_chan_synchronize(struct dma_chan *dc) in tegra_dma_chan_synchronize() argument
1254 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_chan_synchronize()
1256 synchronize_irq(tdc->irq); in tegra_dma_chan_synchronize()
1257 vchan_synchronize(&tdc->vc); in tegra_dma_chan_synchronize()
1260 static void tegra_dma_free_chan_resources(struct dma_chan *dc) in tegra_dma_free_chan_resources() argument
1262 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources()
1264 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1266 tegra_dma_terminate_all(dc); in tegra_dma_free_chan_resources()
1267 synchronize_irq(tdc->irq); in tegra_dma_free_chan_resources()
1269 tasklet_kill(&tdc->vc.task); in tegra_dma_free_chan_resources()
1270 tdc->config_init = false; in tegra_dma_free_chan_resources()
1271 tdc->slave_id = -1; in tegra_dma_free_chan_resources()
1272 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_free_chan_resources()
1273 free_irq(tdc->irq, tdc); in tegra_dma_free_chan_resources()
1275 vchan_free_chan_resources(&tdc->vc); in tegra_dma_free_chan_resources()
1281 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
1285 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1290 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1321 .compatible = "nvidia,tegra186-gpcdma",
1324 .compatible = "nvidia,tegra194-gpcdma",
1327 .compatible = "nvidia,tegra234-gpcdma",
1356 cdata = of_device_get_match_data(&pdev->dev); in tegra_dma_probe()
1358 tdma = devm_kzalloc(&pdev->dev, in tegra_dma_probe()
1359 struct_size(tdma, channels, cdata->nr_channels), in tegra_dma_probe()
1362 return -ENOMEM; in tegra_dma_probe()
1364 tdma->dev = &pdev->dev; in tegra_dma_probe()
1365 tdma->chip_data = cdata; in tegra_dma_probe()
1368 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_dma_probe()
1369 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1370 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1372 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); in tegra_dma_probe()
1373 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1374 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), in tegra_dma_probe()
1377 reset_control_reset(tdma->rst); in tegra_dma_probe()
1379 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1381 iommu_spec = dev_iommu_fwspec_get(&pdev->dev); in tegra_dma_probe()
1383 dev_err(&pdev->dev, "Missing iommu stream-id\n"); in tegra_dma_probe()
1384 return -EINVAL; in tegra_dma_probe()
1386 stream_id = iommu_spec->ids[0] & 0xffff; in tegra_dma_probe()
1388 ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", in tegra_dma_probe()
1389 &tdma->chan_mask); in tegra_dma_probe()
1391 dev_warn(&pdev->dev, in tegra_dma_probe()
1392 "Missing dma-channel-mask property, using default channel mask %#x\n", in tegra_dma_probe()
1394 tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; in tegra_dma_probe()
1397 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1398 for (i = 0; i < cdata->nr_channels; i++) { in tegra_dma_probe()
1399 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1402 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_probe()
1405 tdc->irq = platform_get_irq(pdev, i); in tegra_dma_probe()
1406 if (tdc->irq < 0) in tegra_dma_probe()
1407 return tdc->irq; in tegra_dma_probe()
1409 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + in tegra_dma_probe()
1410 i * cdata->channel_reg_size; in tegra_dma_probe()
1411 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); in tegra_dma_probe()
1412 tdc->tdma = tdma; in tegra_dma_probe()
1413 tdc->id = i; in tegra_dma_probe()
1414 tdc->slave_id = -1; in tegra_dma_probe()
1416 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_dma_probe()
1417 tdc->vc.desc_free = tegra_dma_desc_free; in tegra_dma_probe()
1419 /* program stream-id for this channel */ in tegra_dma_probe()
1421 tdc->stream_id = stream_id; in tegra_dma_probe()
1424 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1425 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1426 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1427 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1428 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1434 tdma->dma_dev.copy_align = 2; in tegra_dma_probe()
1435 tdma->dma_dev.fill_align = 2; in tegra_dma_probe()
1436 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1438 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1440 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1441 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy; in tegra_dma_probe()
1442 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset; in tegra_dma_probe()
1443 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1444 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1445 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1446 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1447 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1448 tdma->dma_dev.device_pause = tegra_dma_device_pause; in tegra_dma_probe()
1449 tdma->dma_dev.device_resume = tegra_dma_device_resume; in tegra_dma_probe()
1450 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize; in tegra_dma_probe()
1451 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in tegra_dma_probe()
1453 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1455 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1460 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_dma_probe()
1463 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1466 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1470 dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", in tegra_dma_probe()
1471 hweight_long(tdma->chan_mask)); in tegra_dma_probe()
1480 of_dma_controller_free(pdev->dev.of_node); in tegra_dma_remove()
1481 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1491 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_suspend()
1492 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend()
1494 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_suspend()
1497 if (tdc->dma_desc) { in tegra_dma_pm_suspend()
1498 dev_err(tdma->dev, "channel %u busy\n", i); in tegra_dma_pm_suspend()
1499 return -EBUSY; in tegra_dma_pm_suspend()
1511 reset_control_reset(tdma->rst); in tegra_dma_pm_resume()
1513 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_resume()
1514 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume()
1516 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_resume()
1519 tegra_dma_program_sid(tdc, tdc->stream_id); in tegra_dma_pm_resume()
1531 .name = "tegra-gpcdma",