Lines Matching +full:standard +full:- +full:mode

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) ST-Ericsson SA 2007-2010
4  * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
20 #define D40_PHYS_TO_GROUP(phys) ((phys & (D40_GROUP_SIZE - 1)) / 2)
22 /* Most bits of the CFG register are the same in log as in phy mode */
38 /* Standard channel parameters - basic mode (element register) */
44 /* Standard channel parameters - basic mode (Link register) */
50  * 29-bit byte word aligned address of the reload area.
54 /* Standard basic channel logical mode */
68 /* Standard basic channel logical params in memory */
114 /* Standard channel parameter register offsets */
329  * struct d40_phy_lli - The basic configuration register for each physical
339  * physical(standard) mode.
352  * struct d40_phy_lli_bidir - struct for a transfer.
367  * struct d40_log_lli - logical lli configuration
382  * struct d40_log_lli_bidir - For both src and dst
396  * struct d40_log_lli_full - LCPA layout
398  * @lcsp0: Logical Channel Standard Param 0 - Src.
399  * @lcsp1: Logical Channel Standard Param 1 - Src.
400  * @lcsp2: Logical Channel Standard Param 2 - Dst.
401  * @lcsp3: Logical Channel Standard Param 3 - Dst.
414  * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings