Lines Matching +full:0 +full:xeb4
10 #define D40_DREG_PCBASE 0x400
35 #define D40_SREG_CFG_PHY_EVTL_POS 0
40 #define D40_SREG_ELEM_PHY_EIDX_POS 0
42 #define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
45 #define D40_SREG_LNK_PHY_TCP_POS 0
52 #define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
60 #define D40_SREG_ELEM_LOG_TCP_POS 0
62 #define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
66 #define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
72 #define D40_MEM_LCSP0_SPTR_POS 0
74 #define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
75 #define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
86 #define D40_MEM_LCSP1_STCP_POS 0
88 #define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
89 #define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
90 #define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
91 #define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
92 #define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
93 #define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
98 #define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
108 #define D40_MEM_LCSP3_DTCP_POS 0
110 #define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
111 #define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
115 #define D40_CHAN_REG_SSCFG 0x00
116 #define D40_CHAN_REG_SSELT 0x04
117 #define D40_CHAN_REG_SSPTR 0x08
118 #define D40_CHAN_REG_SSLNK 0x0C
119 #define D40_CHAN_REG_SDCFG 0x10
120 #define D40_CHAN_REG_SDELT 0x14
121 #define D40_CHAN_REG_SDPTR 0x18
122 #define D40_CHAN_REG_SDLNK 0x1C
125 #define D40_DREG_GCC 0x000
126 #define D40_DREG_GCC_ENA 0x1
128 #define D40_DREG_GCC_ENABLE_ALL 0x3ff01
130 #define D40_DREG_GCC_SRC 0
135 #define D40_DREG_PRTYP 0x004
136 #define D40_DREG_PRSME 0x008
137 #define D40_DREG_PRSMO 0x00C
138 #define D40_DREG_PRMSE 0x010
139 #define D40_DREG_PRMSO 0x014
140 #define D40_DREG_PRMOE 0x018
141 #define D40_DREG_PRMOO 0x01C
142 #define D40_DREG_PRMO_PCHAN_BASIC 0x1
143 #define D40_DREG_PRMO_PCHAN_MODULO 0x2
144 #define D40_DREG_PRMO_PCHAN_DOUBLE_DST 0x3
145 #define D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG 0x1
146 #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY 0x2
147 #define D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG 0x3
149 #define D40_DREG_LCPA 0x020
150 #define D40_DREG_LCLA 0x024
152 #define D40_DREG_SSEG1 0x030
153 #define D40_DREG_SSEG2 0x034
154 #define D40_DREG_SSEG3 0x038
155 #define D40_DREG_SSEG4 0x03C
157 #define D40_DREG_SCEG1 0x040
158 #define D40_DREG_SCEG2 0x044
159 #define D40_DREG_SCEG3 0x048
160 #define D40_DREG_SCEG4 0x04C
162 #define D40_DREG_ACTIVE 0x050
163 #define D40_DREG_ACTIVO 0x054
164 #define D40_DREG_CIDMOD 0x058
165 #define D40_DREG_TCIDV 0x05C
166 #define D40_DREG_PCMIS 0x060
167 #define D40_DREG_PCICR 0x064
168 #define D40_DREG_PCTIS 0x068
169 #define D40_DREG_PCEIS 0x06C
171 #define D40_DREG_SPCMIS 0x070
172 #define D40_DREG_SPCICR 0x074
173 #define D40_DREG_SPCTIS 0x078
174 #define D40_DREG_SPCEIS 0x07C
176 #define D40_DREG_LCMIS0 0x080
177 #define D40_DREG_LCMIS1 0x084
178 #define D40_DREG_LCMIS2 0x088
179 #define D40_DREG_LCMIS3 0x08C
180 #define D40_DREG_LCICR0 0x090
181 #define D40_DREG_LCICR1 0x094
182 #define D40_DREG_LCICR2 0x098
183 #define D40_DREG_LCICR3 0x09C
184 #define D40_DREG_LCTIS0 0x0A0
185 #define D40_DREG_LCTIS1 0x0A4
186 #define D40_DREG_LCTIS2 0x0A8
187 #define D40_DREG_LCTIS3 0x0AC
188 #define D40_DREG_LCEIS0 0x0B0
189 #define D40_DREG_LCEIS1 0x0B4
190 #define D40_DREG_LCEIS2 0x0B8
191 #define D40_DREG_LCEIS3 0x0BC
193 #define D40_DREG_SLCMIS1 0x0C0
194 #define D40_DREG_SLCMIS2 0x0C4
195 #define D40_DREG_SLCMIS3 0x0C8
196 #define D40_DREG_SLCMIS4 0x0CC
198 #define D40_DREG_SLCICR1 0x0D0
199 #define D40_DREG_SLCICR2 0x0D4
200 #define D40_DREG_SLCICR3 0x0D8
201 #define D40_DREG_SLCICR4 0x0DC
203 #define D40_DREG_SLCTIS1 0x0E0
204 #define D40_DREG_SLCTIS2 0x0E4
205 #define D40_DREG_SLCTIS3 0x0E8
206 #define D40_DREG_SLCTIS4 0x0EC
208 #define D40_DREG_SLCEIS1 0x0F0
209 #define D40_DREG_SLCEIS2 0x0F4
210 #define D40_DREG_SLCEIS3 0x0F8
211 #define D40_DREG_SLCEIS4 0x0FC
213 #define D40_DREG_FSESS1 0x100
214 #define D40_DREG_FSESS2 0x104
216 #define D40_DREG_FSEBS1 0x108
217 #define D40_DREG_FSEBS2 0x10C
219 #define D40_DREG_PSEG1 0x110
220 #define D40_DREG_PSEG2 0x114
221 #define D40_DREG_PSEG3 0x118
222 #define D40_DREG_PSEG4 0x11C
223 #define D40_DREG_PCEG1 0x120
224 #define D40_DREG_PCEG2 0x124
225 #define D40_DREG_PCEG3 0x128
226 #define D40_DREG_PCEG4 0x12C
227 #define D40_DREG_RSEG1 0x130
228 #define D40_DREG_RSEG2 0x134
229 #define D40_DREG_RSEG3 0x138
230 #define D40_DREG_RSEG4 0x13C
231 #define D40_DREG_RCEG1 0x140
232 #define D40_DREG_RCEG2 0x144
233 #define D40_DREG_RCEG3 0x148
234 #define D40_DREG_RCEG4 0x14C
236 #define D40_DREG_PREFOT 0x15C
237 #define D40_DREG_EXTCFG 0x160
239 #define D40_DREG_CPSEG1 0x200
240 #define D40_DREG_CPSEG2 0x204
241 #define D40_DREG_CPSEG3 0x208
242 #define D40_DREG_CPSEG4 0x20C
243 #define D40_DREG_CPSEG5 0x210
245 #define D40_DREG_CPCEG1 0x220
246 #define D40_DREG_CPCEG2 0x224
247 #define D40_DREG_CPCEG3 0x228
248 #define D40_DREG_CPCEG4 0x22C
249 #define D40_DREG_CPCEG5 0x230
251 #define D40_DREG_CRSEG1 0x240
252 #define D40_DREG_CRSEG2 0x244
253 #define D40_DREG_CRSEG3 0x248
254 #define D40_DREG_CRSEG4 0x24C
255 #define D40_DREG_CRSEG5 0x250
257 #define D40_DREG_CRCEG1 0x260
258 #define D40_DREG_CRCEG2 0x264
259 #define D40_DREG_CRCEG3 0x268
260 #define D40_DREG_CRCEG4 0x26C
261 #define D40_DREG_CRCEG5 0x270
263 #define D40_DREG_CFSESS1 0x280
264 #define D40_DREG_CFSESS2 0x284
265 #define D40_DREG_CFSESS3 0x288
267 #define D40_DREG_CFSEBS1 0x290
268 #define D40_DREG_CFSEBS2 0x294
269 #define D40_DREG_CFSEBS3 0x298
271 #define D40_DREG_CLCMIS1 0x300
272 #define D40_DREG_CLCMIS2 0x304
273 #define D40_DREG_CLCMIS3 0x308
274 #define D40_DREG_CLCMIS4 0x30C
275 #define D40_DREG_CLCMIS5 0x310
277 #define D40_DREG_CLCICR1 0x320
278 #define D40_DREG_CLCICR2 0x324
279 #define D40_DREG_CLCICR3 0x328
280 #define D40_DREG_CLCICR4 0x32C
281 #define D40_DREG_CLCICR5 0x330
283 #define D40_DREG_CLCTIS1 0x340
284 #define D40_DREG_CLCTIS2 0x344
285 #define D40_DREG_CLCTIS3 0x348
286 #define D40_DREG_CLCTIS4 0x34C
287 #define D40_DREG_CLCTIS5 0x350
289 #define D40_DREG_CLCEIS1 0x360
290 #define D40_DREG_CLCEIS2 0x364
291 #define D40_DREG_CLCEIS3 0x368
292 #define D40_DREG_CLCEIS4 0x36C
293 #define D40_DREG_CLCEIS5 0x370
295 #define D40_DREG_CPCMIS 0x380
296 #define D40_DREG_CPCICR 0x384
297 #define D40_DREG_CPCTIS 0x388
298 #define D40_DREG_CPCEIS 0x38C
300 #define D40_DREG_SCCIDA1 0xE80
301 #define D40_DREG_SCCIDA2 0xE90
302 #define D40_DREG_SCCIDA3 0xEA0
303 #define D40_DREG_SCCIDA4 0xEB0
304 #define D40_DREG_SCCIDA5 0xEC0
306 #define D40_DREG_SCCIDB1 0xE84
307 #define D40_DREG_SCCIDB2 0xE94
308 #define D40_DREG_SCCIDB3 0xEA4
309 #define D40_DREG_SCCIDB4 0xEB4
310 #define D40_DREG_SCCIDB5 0xEC4
312 #define D40_DREG_PRSCCIDA 0xF80
313 #define D40_DREG_PRSCCIDB 0xF84
315 #define D40_DREG_STFU 0xFC8
316 #define D40_DREG_ICFG 0xFCC
317 #define D40_DREG_PERIPHID0 0xFE0
318 #define D40_DREG_PERIPHID1 0xFE4
319 #define D40_DREG_PERIPHID2 0xFE8
320 #define D40_DREG_PERIPHID3 0xFEC
321 #define D40_DREG_CELLID0 0xFF0
322 #define D40_DREG_CELLID1 0xFF4
323 #define D40_DREG_CELLID2 0xFF8
324 #define D40_DREG_CELLID3 0xFFC
398 * @lcsp0: Logical Channel Standard Param 0 - Src.
427 LLI_ADDR_INC = 1 << 0,