597 	void __iomem			 *virtbase;  member
645 	return chan->base->virtbase + D40_DREG_PCBASE +  in chan_base()
1082 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_phy()
1084 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_phy()
1299 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_log()
1301 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_log()
1383 	writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);  in d40_config_write()
1388 	writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);  in d40_config_write()
1680 		regs[i] = readl(base->virtbase + il[i].src);  in d40_handle_interrupt()
1708 		writel(BIT(idx), base->virtbase + il[row].clr);  in d40_handle_interrupt()
2086 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in d40_is_paused()
2088 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in d40_is_paused()
2345 	writel(bit, d40c->base->virtbase + prioreg + group * 4);  in __d40_set_prio_rt()
2346 	writel(bit, d40c->base->virtbase + rtreg + group * 4);  in __d40_set_prio_rt()
2986 		addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;  in d40_save_restore_registers()
2996 	dma40_backup(base->virtbase, base->reg_val_backup,  in d40_save_restore_registers()
3002 		dma40_backup(base->virtbase, base->reg_val_backup_v4,  in d40_save_restore_registers()
3017 			       base->virtbase + D40_DREG_GCC);  in dma40_runtime_suspend()
3029 		       base->virtbase + D40_DREG_GCC);  in dma40_runtime_resume()
3051 	val[0] = readl(base->virtbase + D40_DREG_PRSME);  in d40_phy_res_init()
3052 	val[1] = readl(base->virtbase + D40_DREG_PRSMO);  in d40_phy_res_init()
3102 	val[0] = readl(base->virtbase + D40_DREG_PRTYP);  in d40_phy_res_init()
3121 	writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_phy_res_init()
3141 	void __iomem *virtbase;  in d40_hw_detect_init()  local
3157 	virtbase = devm_platform_ioremap_resource_byname(pdev, "base");  in d40_hw_detect_init()
3158 	if (IS_ERR(virtbase))  in d40_hw_detect_init()
3159 		return PTR_ERR(virtbase);  in d40_hw_detect_init()
3163 		pid |= (readl(virtbase + SZ_4K - 0x20 + 4 * i)  in d40_hw_detect_init()
3166 		cid |= (readl(virtbase + SZ_4K - 0x10 + 4 * i)  in d40_hw_detect_init()
3198 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;  in d40_hw_detect_init()
3225 	base->virtbase = virtbase;  in d40_hw_detect_init()
3327 		       base->virtbase + dma_init_reg[i].reg);  in d40_hw_init()
3352 	writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);  in d40_hw_init()
3353 	writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);  in d40_hw_init()
3354 	writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);  in d40_hw_init()
3355 	writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);  in d40_hw_init()
3358 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);  in d40_hw_init()
3361 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);  in d40_hw_init()
3444 	       base->virtbase + D40_DREG_LCLA);  in d40_lcla_allocate()
3549 	val = readl(base->virtbase + D40_DREG_LCPA);  in d40_probe()
3555 		writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA);  in d40_probe()
3580 		writel(res->start, base->virtbase + D40_DREG_LCLA);  in d40_probe()
3624 	writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_probe()