Lines Matching +full:gpi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <linux/dma-mapping.h>
14 #include <linux/dma/qcom-gpi-dma.h>
18 #include "../virt-dma.h"
68 /* Register offsets from gpi-top */
181 /* GPII specific Global - Enable bit register */
186 /* GPII general interrupt - Enable bit register */
381 [CONFIG_STATE] = "CONFIG",
473 u32 max_gpii; /* maximum # of gpii instances available per gpi block */
498 void *config; member
506 void __iomem *regs; /* points to gpi top */
558 return ring->phys_addr + (addr - ring->base); in to_physical()
563 return ring->base + (addr - ring->phys_addr); in to_virtual()
576 /* gpi_write_reg_field - write to specific bit field */
590 void __iomem *addr = gpii->regs + offset; in gpi_update_reg()
601 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
603 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
605 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
607 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
609 gpi_update_reg(gpii, GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
611 gpi_update_reg(gpii, GPII_n_CNTXT_GPII_IRQ_EN_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
613 gpi_update_reg(gpii, GPII_n_CNTXT_INTSET_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
616 gpii->cntxt_type_irq_msk = 0; in gpi_disable_interrupts()
617 devm_free_irq(gpii->gpi_dev->dev, gpii->irq, gpii); in gpi_disable_interrupts()
618 gpii->configured_irq = false; in gpi_disable_interrupts()
631 if (!gpii->configured_irq) { in gpi_config_interrupts()
632 ret = devm_request_irq(gpii->gpi_dev->dev, gpii->irq, in gpi_config_interrupts()
634 "gpi-dma", gpii); in gpi_config_interrupts()
636 dev_err(gpii->gpi_dev->dev, "error request irq:%d ret:%d\n", in gpi_config_interrupts()
637 gpii->irq, ret); in gpi_config_interrupts()
648 gpii->cntxt_type_irq_msk |= GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB; in gpi_config_interrupts()
650 gpii->cntxt_type_irq_msk &= ~(GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB); in gpi_config_interrupts()
651 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
652 GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK, gpii->cntxt_type_irq_msk); in gpi_config_interrupts()
654 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
656 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
659 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
662 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
665 gpi_update_reg(gpii, GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(gpii->gpii_id), in gpi_config_interrupts()
668 gpi_update_reg(gpii, GPII_n_CNTXT_GPII_IRQ_EN_OFFS(gpii->gpii_id), in gpi_config_interrupts()
670 gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_LSB_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
671 gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_MSB_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
672 gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_0_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
673 gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_1_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
674 gpi_update_reg(gpii, GPII_n_CNTXT_INTSET_OFFS(gpii->gpii_id), in gpi_config_interrupts()
676 gpi_update_reg(gpii, GPII_n_ERROR_LOG_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
678 gpii->cntxt_type_irq_msk = enable; in gpi_config_interrupts()
681 gpii->configured_irq = true; in gpi_config_interrupts()
695 return -EINVAL; in gpi_send_cmd()
697 chid = gchan->chid; in gpi_send_cmd()
699 dev_dbg(gpii->gpi_dev->dev, in gpi_send_cmd()
703 reinit_completion(&gpii->cmd_completion); in gpi_send_cmd()
704 gpii->gpi_cmd = gpi_cmd; in gpi_send_cmd()
706 cmd_reg = IS_CHAN_CMD(gpi_cmd) ? gchan->ch_cmd_reg : gpii->ev_cmd_reg; in gpi_send_cmd()
710 timeout = wait_for_completion_timeout(&gpii->cmd_completion, in gpi_send_cmd()
713 dev_err(gpii->gpi_dev->dev, "cmd: %s completion timeout:%u\n", in gpi_send_cmd()
715 return -EIO; in gpi_send_cmd()
722 if (IS_CHAN_CMD(gpi_cmd) && gchan->ch_state == gpi_cmd_info[gpi_cmd].state) in gpi_send_cmd()
725 if (!IS_CHAN_CMD(gpi_cmd) && gpii->ev_state == gpi_cmd_info[gpi_cmd].state) in gpi_send_cmd()
728 return -EIO; in gpi_send_cmd()
735 struct gpii *gpii = gchan->gpii; in gpi_write_ch_db()
739 gpi_write_reg(gpii, gchan->ch_cntxt_db_reg, p_wp); in gpi_write_ch_db()
748 p_wp = ring->phys_addr + (wp - ring->base); in gpi_write_ev_db()
749 gpi_write_reg(gpii, gpii->ev_cntxt_db_reg, p_wp); in gpi_write_ev_db()
755 gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0)); in gpi_process_ieob()
758 tasklet_hi_schedule(&gpii->ev_task); in gpi_process_ieob()
764 u32 gpii_id = gpii->gpii_id; in gpi_process_ch_ctrl_irq()
766 u32 ch_irq = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_ch_ctrl_irq()
772 gpi_write_reg(gpii, gpii->regs + offset, (u32)ch_irq); in gpi_process_ch_ctrl_irq()
778 gchan = &gpii->gchan[chid]; in gpi_process_ch_ctrl_irq()
779 state = gpi_read_reg(gpii, gchan->ch_cntxt_base_reg + in gpi_process_ch_ctrl_irq()
788 if (gpii->gpi_cmd == GPI_CH_CMD_DE_ALLOC) in gpi_process_ch_ctrl_irq()
790 gchan->ch_state = state; in gpi_process_ch_ctrl_irq()
797 if (gchan->ch_state != CH_STATE_STOP_IN_PROC) in gpi_process_ch_ctrl_irq()
798 complete_all(&gpii->cmd_completion); in gpi_process_ch_ctrl_irq()
802 /* processing gpi general error interrupts */
805 u32 gpii_id = gpii->gpii_id; in gpi_process_gen_err_irq()
807 u32 irq_stts = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_gen_err_irq()
810 dev_dbg(gpii->gpi_dev->dev, "irq_stts:0x%x\n", irq_stts); in gpi_process_gen_err_irq()
814 gpi_write_reg(gpii, gpii->regs + offset, irq_stts); in gpi_process_gen_err_irq()
817 /* processing gpi level error interrupts */
820 u32 gpii_id = gpii->gpii_id; in gpi_process_glob_err_irq()
822 u32 irq_stts = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_glob_err_irq()
825 gpi_write_reg(gpii, gpii->regs + offset, irq_stts); in gpi_process_glob_err_irq()
829 dev_err(gpii->gpi_dev->dev, "invalid error status:0x%x\n", irq_stts); in gpi_process_glob_err_irq()
834 gpi_write_reg(gpii, gpii->regs + offset, 0); in gpi_process_glob_err_irq()
841 u32 gpii_id = gpii->gpii_id; in gpi_handle_irq()
845 read_lock_irqsave(&gpii->pm_lock, flags); in gpi_handle_irq()
851 if (!REG_ACCESS_VALID(gpii->pm_state)) { in gpi_handle_irq()
852 dev_err(gpii->gpi_dev->dev, "receive interrupt while in %s state\n", in gpi_handle_irq()
853 TO_GPI_PM_STR(gpii->pm_state)); in gpi_handle_irq()
857 offset = GPII_n_CNTXT_TYPE_IRQ_OFFS(gpii->gpii_id); in gpi_handle_irq()
858 type = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
878 dev_dbg(gpii->gpi_dev->dev, in gpi_handle_irq()
881 ev_ch_irq = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
885 gpi_write_reg(gpii, gpii->regs + offset, ev_ch_irq); in gpi_handle_irq()
886 ev_state = gpi_read_reg(gpii, gpii->ev_cntxt_base_reg + in gpi_handle_irq()
895 if (gpii->gpi_cmd == GPI_EV_CMD_DEALLOC) in gpi_handle_irq()
898 gpii->ev_state = ev_state; in gpi_handle_irq()
899 dev_dbg(gpii->gpi_dev->dev, "setting EV state to %s\n", in gpi_handle_irq()
900 TO_GPI_EV_STATE_STR(gpii->ev_state)); in gpi_handle_irq()
901 complete_all(&gpii->cmd_completion); in gpi_handle_irq()
907 dev_dbg(gpii->gpi_dev->dev, "process CH CTRL interrupts\n"); in gpi_handle_irq()
913 dev_err(gpii->gpi_dev->dev, "Unhandled interrupt status:0x%x\n", type); in gpi_handle_irq()
918 offset = GPII_n_CNTXT_TYPE_IRQ_OFFS(gpii->gpii_id); in gpi_handle_irq()
919 type = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
923 read_unlock_irqrestore(&gpii->pm_lock, flags); in gpi_handle_irq()
932 struct gpii *gpii = gchan->gpii; in gpi_process_imed_data_event()
933 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_process_imed_data_event()
934 void *tre = ch_ring->base + (ch_ring->el_size * imed_event->tre_index); in gpi_process_imed_data_event()
944 if (gchan->pm_state != ACTIVE_STATE) { in gpi_process_imed_data_event()
945 dev_err(gpii->gpi_dev->dev, "skipping processing event because ch @ %s state\n", in gpi_process_imed_data_event()
946 TO_GPI_PM_STR(gchan->pm_state)); in gpi_process_imed_data_event()
950 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
951 vd = vchan_next_desc(&gchan->vc); in gpi_process_imed_data_event()
956 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
957 dev_dbg(gpii->gpi_dev->dev, "event without a pending descriptor!\n"); in gpi_process_imed_data_event()
959 dev_dbg(gpii->gpi_dev->dev, in gpi_process_imed_data_event()
961 gpi_ere->dword[0], gpi_ere->dword[1], in gpi_process_imed_data_event()
962 gpi_ere->dword[2], gpi_ere->dword[3]); in gpi_process_imed_data_event()
964 dev_dbg(gpii->gpi_dev->dev, in gpi_process_imed_data_event()
966 gpi_tre->dword[0], gpi_tre->dword[1], in gpi_process_imed_data_event()
967 gpi_tre->dword[2], gpi_tre->dword[3]); in gpi_process_imed_data_event()
971 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
977 tre += ch_ring->el_size; in gpi_process_imed_data_event()
978 if (tre >= (ch_ring->base + ch_ring->len)) in gpi_process_imed_data_event()
979 tre = ch_ring->base; in gpi_process_imed_data_event()
980 ch_ring->rp = tre; in gpi_process_imed_data_event()
985 chid = imed_event->chid; in gpi_process_imed_data_event()
986 if (imed_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { in gpi_process_imed_data_event()
993 if (imed_event->code == MSM_GPI_TCE_UNEXP_ERR) in gpi_process_imed_data_event()
997 result.residue = gpi_desc->len - imed_event->length; in gpi_process_imed_data_event()
999 dma_cookie_complete(&vd->tx); in gpi_process_imed_data_event()
1000 dmaengine_desc_get_callback_invoke(&vd->tx, &result); in gpi_process_imed_data_event()
1003 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
1004 list_del(&vd->node); in gpi_process_imed_data_event()
1005 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
1014 struct gpii *gpii = gchan->gpii; in gpi_process_xfer_compl_event()
1015 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_process_xfer_compl_event()
1016 void *ev_rp = to_virtual(ch_ring, compl_event->ptr); in gpi_process_xfer_compl_event()
1024 if (unlikely(gchan->pm_state != ACTIVE_STATE)) { in gpi_process_xfer_compl_event()
1025 dev_err(gpii->gpi_dev->dev, "skipping processing event because ch @ %s state\n", in gpi_process_xfer_compl_event()
1026 TO_GPI_PM_STR(gchan->pm_state)); in gpi_process_xfer_compl_event()
1030 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1031 vd = vchan_next_desc(&gchan->vc); in gpi_process_xfer_compl_event()
1035 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1036 dev_err(gpii->gpi_dev->dev, "Event without a pending descriptor!\n"); in gpi_process_xfer_compl_event()
1038 dev_err(gpii->gpi_dev->dev, in gpi_process_xfer_compl_event()
1040 gpi_ere->dword[0], gpi_ere->dword[1], in gpi_process_xfer_compl_event()
1041 gpi_ere->dword[2], gpi_ere->dword[3]); in gpi_process_xfer_compl_event()
1046 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1052 ev_rp += ch_ring->el_size; in gpi_process_xfer_compl_event()
1053 if (ev_rp >= (ch_ring->base + ch_ring->len)) in gpi_process_xfer_compl_event()
1054 ev_rp = ch_ring->base; in gpi_process_xfer_compl_event()
1055 ch_ring->rp = ev_rp; in gpi_process_xfer_compl_event()
1060 chid = compl_event->chid; in gpi_process_xfer_compl_event()
1061 if (compl_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { in gpi_process_xfer_compl_event()
1068 if (compl_event->code == MSM_GPI_TCE_UNEXP_ERR) { in gpi_process_xfer_compl_event()
1069 dev_err(gpii->gpi_dev->dev, "Error in Transaction\n"); in gpi_process_xfer_compl_event()
1072 dev_dbg(gpii->gpi_dev->dev, "Transaction Success\n"); in gpi_process_xfer_compl_event()
1075 result.residue = gpi_desc->len - compl_event->length; in gpi_process_xfer_compl_event()
1076 dev_dbg(gpii->gpi_dev->dev, "Residue %d\n", result.residue); in gpi_process_xfer_compl_event()
1078 dma_cookie_complete(&vd->tx); in gpi_process_xfer_compl_event()
1079 dmaengine_desc_get_callback_invoke(&vd->tx, &result); in gpi_process_xfer_compl_event()
1082 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1083 list_del(&vd->node); in gpi_process_xfer_compl_event()
1084 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1092 struct gpi_ring *ev_ring = &gpii->ev_ring; in gpi_process_events()
1099 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_process_events()
1103 while (rp != ev_ring->rp) { in gpi_process_events()
1104 gpi_event = ev_ring->rp; in gpi_process_events()
1105 chid = gpi_event->xfer_compl_event.chid; in gpi_process_events()
1106 type = gpi_event->xfer_compl_event.type; in gpi_process_events()
1108 dev_dbg(gpii->gpi_dev->dev, in gpi_process_events()
1110 chid, type, gpi_event->gpi_ere.dword[0], in gpi_process_events()
1111 gpi_event->gpi_ere.dword[1], gpi_event->gpi_ere.dword[2], in gpi_process_events()
1112 gpi_event->gpi_ere.dword[3]); in gpi_process_events()
1116 gchan = &gpii->gchan[chid]; in gpi_process_events()
1118 &gpi_event->xfer_compl_event); in gpi_process_events()
1121 dev_dbg(gpii->gpi_dev->dev, "stale event, not processing\n"); in gpi_process_events()
1124 gchan = &gpii->gchan[chid]; in gpi_process_events()
1126 &gpi_event->immediate_data_event); in gpi_process_events()
1129 dev_dbg(gpii->gpi_dev->dev, "QUP_NOTIF_EV_TYPE\n"); in gpi_process_events()
1132 dev_dbg(gpii->gpi_dev->dev, in gpi_process_events()
1137 gpi_write_ev_db(gpii, ev_ring, ev_ring->wp); in gpi_process_events()
1140 gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0)); in gpi_process_events()
1142 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_process_events()
1145 } while (rp != ev_ring->rp); in gpi_process_events()
1153 read_lock(&gpii->pm_lock); in gpi_ev_tasklet()
1154 if (!REG_ACCESS_VALID(gpii->pm_state)) { in gpi_ev_tasklet()
1155 read_unlock(&gpii->pm_lock); in gpi_ev_tasklet()
1156 dev_err(gpii->gpi_dev->dev, "not processing any events, pm_state:%s\n", in gpi_ev_tasklet()
1157 TO_GPI_PM_STR(gpii->pm_state)); in gpi_ev_tasklet()
1166 read_unlock(&gpii->pm_lock); in gpi_ev_tasklet()
1172 struct gpii *gpii = gchan->gpii; in gpi_mark_stale_events()
1173 struct gpi_ring *ev_ring = &gpii->ev_ring; in gpi_mark_stale_events()
1177 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_mark_stale_events()
1179 ev_rp = ev_ring->rp; in gpi_mark_stale_events()
1183 u32 chid = gpi_event->xfer_compl_event.chid; in gpi_mark_stale_events()
1185 if (chid == gchan->chid) in gpi_mark_stale_events()
1186 gpi_event->xfer_compl_event.type = STALE_EV_TYPE; in gpi_mark_stale_events()
1187 ev_rp += ev_ring->el_size; in gpi_mark_stale_events()
1188 if (ev_rp >= (ev_ring->base + ev_ring->len)) in gpi_mark_stale_events()
1189 ev_rp = ev_ring->base; in gpi_mark_stale_events()
1190 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_mark_stale_events()
1195 /* reset sw state and issue channel reset or de-alloc */
1198 struct gpii *gpii = gchan->gpii; in gpi_reset_chan()
1199 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_reset_chan()
1206 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_reset_chan()
1212 ch_ring->rp = ch_ring->base; in gpi_reset_chan()
1213 ch_ring->wp = ch_ring->base; in gpi_reset_chan()
1219 write_lock_irq(&gpii->pm_lock); in gpi_reset_chan()
1223 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_reset_chan()
1224 vchan_get_all_descriptors(&gchan->vc, &list); in gpi_reset_chan()
1225 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_reset_chan()
1226 write_unlock_irq(&gpii->pm_lock); in gpi_reset_chan()
1227 vchan_dma_desc_free_list(&gchan->vc, &list); in gpi_reset_chan()
1234 struct gpii *gpii = gchan->gpii; in gpi_start_chan()
1239 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_start_chan()
1245 write_lock_irq(&gpii->pm_lock); in gpi_start_chan()
1246 gchan->pm_state = ACTIVE_STATE; in gpi_start_chan()
1247 write_unlock_irq(&gpii->pm_lock); in gpi_start_chan()
1254 struct gpii *gpii = gchan->gpii; in gpi_stop_chan()
1259 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_stop_chan()
1270 struct gpii *gpii = chan->gpii; in gpi_alloc_chan()
1271 struct gpi_ring *ring = &chan->ch_ring; in gpi_alloc_chan()
1273 u32 id = gpii->gpii_id; in gpi_alloc_chan()
1274 u32 chid = chan->chid; in gpi_alloc_chan()
1280 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_alloc_chan()
1286 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_0_CONFIG, in gpi_alloc_chan()
1287 GPII_n_CH_k_CNTXT_0(ring->el_size, 0, chan->dir, GPI_CHTYPE_PROTO_GPI)); in gpi_alloc_chan()
1288 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_1_R_LENGTH, ring->len); in gpi_alloc_chan()
1289 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_2_RING_BASE_LSB, ring->phys_addr); in gpi_alloc_chan()
1290 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_3_RING_BASE_MSB, in gpi_alloc_chan()
1291 upper_32_bits(ring->phys_addr)); in gpi_alloc_chan()
1292 gpi_write_reg(gpii, chan->ch_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB, in gpi_alloc_chan()
1293 upper_32_bits(ring->phys_addr)); in gpi_alloc_chan()
1294 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid), in gpi_alloc_chan()
1295 GPII_n_CH_k_SCRATCH_0(pair_chid, chan->protocol, chan->seid)); in gpi_alloc_chan()
1296 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0); in gpi_alloc_chan()
1297 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0); in gpi_alloc_chan()
1298 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, chid), 0); in gpi_alloc_chan()
1299 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_QOS_OFFS(id, chid), 1); in gpi_alloc_chan()
1309 struct gpi_ring *ring = &gpii->ev_ring; in gpi_alloc_ev_chan()
1310 void __iomem *base = gpii->ev_cntxt_base_reg; in gpi_alloc_ev_chan()
1315 dev_err(gpii->gpi_dev->dev, "error with cmd:%s ret:%d\n", in gpi_alloc_ev_chan()
1322 GPII_n_EV_k_CNTXT_0(ring->el_size, GPI_INTTYPE_IRQ, GPI_CHTYPE_GPI_EV)); in gpi_alloc_ev_chan()
1323 gpi_write_reg(gpii, base + CNTXT_1_R_LENGTH, ring->len); in gpi_alloc_ev_chan()
1324 gpi_write_reg(gpii, base + CNTXT_2_RING_BASE_LSB, lower_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1325 gpi_write_reg(gpii, base + CNTXT_3_RING_BASE_MSB, upper_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1326 gpi_write_reg(gpii, gpii->ev_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB, in gpi_alloc_ev_chan()
1327 upper_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1336 ring->wp = (ring->base + ring->len - ring->el_size); in gpi_alloc_ev_chan()
1342 write_lock_irq(&gpii->pm_lock); in gpi_alloc_ev_chan()
1343 gpii->pm_state = ACTIVE_STATE; in gpi_alloc_ev_chan()
1344 write_unlock_irq(&gpii->pm_lock); in gpi_alloc_ev_chan()
1345 gpi_write_ev_db(gpii, ring, ring->wp); in gpi_alloc_ev_chan()
1355 if (ring->wp < ring->rp) { in gpi_ring_num_elements_avail()
1356 elements = ((ring->rp - ring->wp) / ring->el_size) - 1; in gpi_ring_num_elements_avail()
1358 elements = (ring->rp - ring->base) / ring->el_size; in gpi_ring_num_elements_avail()
1359 elements += ((ring->base + ring->len - ring->wp) / ring->el_size) - 1; in gpi_ring_num_elements_avail()
1368 return -ENOMEM; in gpi_ring_add_element()
1370 *wp = ring->wp; in gpi_ring_add_element()
1371 ring->wp += ring->el_size; in gpi_ring_add_element()
1372 if (ring->wp >= (ring->base + ring->len)) in gpi_ring_add_element()
1373 ring->wp = ring->base; in gpi_ring_add_element()
1384 ring->wp += ring->el_size; in gpi_ring_recycle_ev_element()
1385 if (ring->wp >= (ring->base + ring->len)) in gpi_ring_recycle_ev_element()
1386 ring->wp = ring->base; in gpi_ring_recycle_ev_element()
1389 ring->rp += ring->el_size; in gpi_ring_recycle_ev_element()
1390 if (ring->rp >= (ring->base + ring->len)) in gpi_ring_recycle_ev_element()
1391 ring->rp = ring->base; in gpi_ring_recycle_ev_element()
1400 dma_free_coherent(gpii->gpi_dev->dev, ring->alloc_size, in gpi_free_ring()
1401 ring->pre_aligned, ring->dma_handle); in gpi_free_ring()
1414 if (((1 << bit) - 1) & len) in gpi_alloc_ring()
1417 ring->alloc_size = (len + (len - 1)); in gpi_alloc_ring()
1418 dev_dbg(gpii->gpi_dev->dev, in gpi_alloc_ring()
1421 ring->alloc_size); in gpi_alloc_ring()
1423 ring->pre_aligned = dma_alloc_coherent(gpii->gpi_dev->dev, in gpi_alloc_ring()
1424 ring->alloc_size, in gpi_alloc_ring()
1425 &ring->dma_handle, GFP_KERNEL); in gpi_alloc_ring()
1426 if (!ring->pre_aligned) { in gpi_alloc_ring()
1427 dev_err(gpii->gpi_dev->dev, "could not alloc size:%zu mem for ring\n", in gpi_alloc_ring()
1428 ring->alloc_size); in gpi_alloc_ring()
1429 return -ENOMEM; in gpi_alloc_ring()
1433 ring->phys_addr = (ring->dma_handle + (len - 1)) & ~(len - 1); in gpi_alloc_ring()
1434 ring->base = ring->pre_aligned + (ring->phys_addr - ring->dma_handle); in gpi_alloc_ring()
1435 ring->rp = ring->base; in gpi_alloc_ring()
1436 ring->wp = ring->base; in gpi_alloc_ring()
1437 ring->len = len; in gpi_alloc_ring()
1438 ring->el_size = el_size; in gpi_alloc_ring()
1439 ring->elements = ring->len / ring->el_size; in gpi_alloc_ring()
1440 memset(ring->base, 0, ring->len); in gpi_alloc_ring()
1441 ring->configured = true; in gpi_alloc_ring()
1446 dev_dbg(gpii->gpi_dev->dev, in gpi_alloc_ring()
1448 &ring->dma_handle, &ring->phys_addr, ring->len, in gpi_alloc_ring()
1449 ring->el_size, ring->elements); in gpi_alloc_ring()
1462 ret = gpi_ring_add_element(&gchan->ch_ring, (void **)&ch_tre); in gpi_queue_xfer()
1464 dev_err(gpii->gpi_dev->dev, "Error adding ring element to xfer ring\n"); in gpi_queue_xfer()
1477 struct gpii *gpii = gchan->gpii; in gpi_terminate_all()
1481 mutex_lock(&gpii->ctrl_lock); in gpi_terminate_all()
1487 schid = (gchan->protocol == QCOM_GPI_UART) ? gchan->chid : 0; in gpi_terminate_all()
1488 echid = (gchan->protocol == QCOM_GPI_UART) ? schid + 1 : MAX_CHANNELS_PER_GPII; in gpi_terminate_all()
1492 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1495 write_lock_irq(&gpii->pm_lock); in gpi_terminate_all()
1496 gchan->pm_state = PREPARE_TERMINATE; in gpi_terminate_all()
1497 write_unlock_irq(&gpii->pm_lock); in gpi_terminate_all()
1505 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1509 dev_err(gpii->gpi_dev->dev, "Error resetting channel ret:%d\n", ret); in gpi_terminate_all()
1516 dev_err(gpii->gpi_dev->dev, "Error alloc_channel ret:%d\n", ret); in gpi_terminate_all()
1523 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1527 dev_err(gpii->gpi_dev->dev, "Error Starting Channel ret:%d\n", ret); in gpi_terminate_all()
1533 mutex_unlock(&gpii->ctrl_lock); in gpi_terminate_all()
1541 struct gpii *gpii = gchan->gpii; in gpi_pause()
1544 mutex_lock(&gpii->ctrl_lock); in gpi_pause()
1550 if (gpii->pm_state == PAUSE_STATE) { in gpi_pause()
1551 dev_dbg(gpii->gpi_dev->dev, "channel is already paused\n"); in gpi_pause()
1552 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1558 ret = gpi_stop_chan(&gpii->gchan[i]); in gpi_pause()
1560 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1565 disable_irq(gpii->irq); in gpi_pause()
1568 tasklet_kill(&gpii->ev_task); in gpi_pause()
1570 write_lock_irq(&gpii->pm_lock); in gpi_pause()
1571 gpii->pm_state = PAUSE_STATE; in gpi_pause()
1572 write_unlock_irq(&gpii->pm_lock); in gpi_pause()
1573 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1582 struct gpii *gpii = gchan->gpii; in gpi_resume()
1585 mutex_lock(&gpii->ctrl_lock); in gpi_resume()
1586 if (gpii->pm_state == ACTIVE_STATE) { in gpi_resume()
1587 dev_dbg(gpii->gpi_dev->dev, "channel is already active\n"); in gpi_resume()
1588 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1592 enable_irq(gpii->irq); in gpi_resume()
1596 ret = gpi_send_cmd(gpii, &gpii->gchan[i], GPI_CH_CMD_START); in gpi_resume()
1598 dev_err(gpii->gpi_dev->dev, "Error starting chan, ret:%d\n", ret); in gpi_resume()
1599 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1604 write_lock_irq(&gpii->pm_lock); in gpi_resume()
1605 gpii->pm_state = ACTIVE_STATE; in gpi_resume()
1606 write_unlock_irq(&gpii->pm_lock); in gpi_resume()
1607 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1621 gpi_peripheral_config(struct dma_chan *chan, struct dma_slave_config *config) in gpi_peripheral_config() argument
1625 if (!config->peripheral_config) in gpi_peripheral_config()
1626 return -EINVAL; in gpi_peripheral_config()
1628 gchan->config = krealloc(gchan->config, config->peripheral_size, GFP_NOWAIT); in gpi_peripheral_config()
1629 if (!gchan->config) in gpi_peripheral_config()
1630 return -ENOMEM; in gpi_peripheral_config()
1632 memcpy(gchan->config, config->peripheral_config, config->peripheral_size); in gpi_peripheral_config()
1640 struct gpi_i2c_config *i2c = chan->config; in gpi_create_i2c_tre()
1641 struct device *dev = chan->gpii->gpi_dev->dev; in gpi_create_i2c_tre()
1647 /* first create config tre if applicable */ in gpi_create_i2c_tre()
1648 if (i2c->set_config) { in gpi_create_i2c_tre()
1649 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1652 tre->dword[0] = u32_encode_bits(i2c->low_count, TRE_I2C_C0_TLOW); in gpi_create_i2c_tre()
1653 tre->dword[0] |= u32_encode_bits(i2c->high_count, TRE_I2C_C0_THIGH); in gpi_create_i2c_tre()
1654 tre->dword[0] |= u32_encode_bits(i2c->cycle_count, TRE_I2C_C0_TCYL); in gpi_create_i2c_tre()
1655 tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_TX_PACK); in gpi_create_i2c_tre()
1656 tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_RX_PACK); in gpi_create_i2c_tre()
1658 tre->dword[1] = 0; in gpi_create_i2c_tre()
1660 tre->dword[2] = u32_encode_bits(i2c->clk_div, TRE_C0_CLK_DIV); in gpi_create_i2c_tre()
1662 tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1663 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_i2c_tre()
1667 if (i2c->op == I2C_WRITE) { in gpi_create_i2c_tre()
1668 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1671 if (i2c->multi_msg) in gpi_create_i2c_tre()
1672 tre->dword[0] = u32_encode_bits(I2C_READ, TRE_I2C_GO_CMD); in gpi_create_i2c_tre()
1674 tre->dword[0] = u32_encode_bits(i2c->op, TRE_I2C_GO_CMD); in gpi_create_i2c_tre()
1676 tre->dword[0] |= u32_encode_bits(i2c->addr, TRE_I2C_GO_ADDR); in gpi_create_i2c_tre()
1677 tre->dword[0] |= u32_encode_bits(i2c->stretch, TRE_I2C_GO_STRETCH); in gpi_create_i2c_tre()
1679 tre->dword[1] = 0; in gpi_create_i2c_tre()
1680 tre->dword[2] = u32_encode_bits(i2c->rx_len, TRE_RX_LEN); in gpi_create_i2c_tre()
1682 tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1684 if (i2c->multi_msg) in gpi_create_i2c_tre()
1685 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_i2c_tre()
1687 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_i2c_tre()
1690 if (i2c->op == I2C_READ || i2c->multi_msg == false) { in gpi_create_i2c_tre()
1692 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1696 tre->dword[0] = lower_32_bits(address); in gpi_create_i2c_tre()
1697 tre->dword[1] = upper_32_bits(address); in gpi_create_i2c_tre()
1699 tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN); in gpi_create_i2c_tre()
1701 tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1702 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); in gpi_create_i2c_tre()
1706 dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], in gpi_create_i2c_tre()
1707 desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); in gpi_create_i2c_tre()
1715 struct gpi_spi_config *spi = chan->config; in gpi_create_spi_tre()
1716 struct device *dev = chan->gpii->gpi_dev->dev; in gpi_create_spi_tre()
1722 /* first create config tre if applicable */ in gpi_create_spi_tre()
1723 if (direction == DMA_MEM_TO_DEV && spi->set_config) { in gpi_create_spi_tre()
1724 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1727 tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ); in gpi_create_spi_tre()
1728 tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK); in gpi_create_spi_tre()
1729 tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL); in gpi_create_spi_tre()
1730 tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA); in gpi_create_spi_tre()
1731 tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK); in gpi_create_spi_tre()
1732 tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK); in gpi_create_spi_tre()
1734 tre->dword[1] = 0; in gpi_create_spi_tre()
1736 tre->dword[2] = u32_encode_bits(spi->clk_div, TRE_C0_CLK_DIV); in gpi_create_spi_tre()
1737 tre->dword[2] |= u32_encode_bits(spi->clk_src, TRE_C0_CLK_SRC); in gpi_create_spi_tre()
1739 tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1740 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1745 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1748 tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG); in gpi_create_spi_tre()
1749 tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS); in gpi_create_spi_tre()
1750 tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD); in gpi_create_spi_tre()
1752 tre->dword[1] = 0; in gpi_create_spi_tre()
1754 tre->dword[2] = u32_encode_bits(spi->rx_len, TRE_RX_LEN); in gpi_create_spi_tre()
1756 tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1757 if (spi->cmd == SPI_RX) { in gpi_create_spi_tre()
1758 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); in gpi_create_spi_tre()
1759 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_spi_tre()
1760 } else if (spi->cmd == SPI_TX) { in gpi_create_spi_tre()
1761 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1763 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1764 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_spi_tre()
1769 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1773 tre->dword[0] = lower_32_bits(address); in gpi_create_spi_tre()
1774 tre->dword[1] = upper_32_bits(address); in gpi_create_spi_tre()
1776 tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN); in gpi_create_spi_tre()
1778 tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1780 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); in gpi_create_spi_tre()
1783 dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], in gpi_create_spi_tre()
1784 desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); in gpi_create_spi_tre()
1796 struct gpii *gpii = gchan->gpii; in gpi_prep_slave_sg()
1797 struct device *dev = gpii->gpi_dev->dev; in gpi_prep_slave_sg()
1798 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_prep_slave_sg()
1804 gpii->ieob_set = false; in gpi_prep_slave_sg()
1806 dev_err(gpii->gpi_dev->dev, "invalid dma direction: %d\n", direction); in gpi_prep_slave_sg()
1816 set_config = *(u32 *)gchan->config; in gpi_prep_slave_sg()
1834 if (gchan->protocol == QCOM_GPI_SPI) { in gpi_prep_slave_sg()
1836 } else if (gchan->protocol == QCOM_GPI_I2C) { in gpi_prep_slave_sg()
1839 dev_err(dev, "invalid peripheral: %d\n", gchan->protocol); in gpi_prep_slave_sg()
1845 gpi_desc->gchan = gchan; in gpi_prep_slave_sg()
1846 gpi_desc->len = sg_dma_len(sgl); in gpi_prep_slave_sg()
1847 gpi_desc->num_tre = i; in gpi_prep_slave_sg()
1849 return vchan_tx_prep(&gchan->vc, &gpi_desc->vd, flags); in gpi_prep_slave_sg()
1856 struct gpii *gpii = gchan->gpii; in gpi_issue_pending()
1860 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_issue_pending()
1864 read_lock_irqsave(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1867 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_issue_pending()
1868 if (vchan_issue_pending(&gchan->vc)) in gpi_issue_pending()
1869 vd = list_last_entry(&gchan->vc.desc_issued, in gpi_issue_pending()
1871 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_issue_pending()
1875 read_unlock_irqrestore(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1880 for (i = 0; i < gpi_desc->num_tre; i++) { in gpi_issue_pending()
1881 tre = &gpi_desc->tre[i]; in gpi_issue_pending()
1885 gpi_desc->db = ch_ring->wp; in gpi_issue_pending()
1886 gpi_write_ch_db(gchan, &gchan->ch_ring, gpi_desc->db); in gpi_issue_pending()
1887 read_unlock_irqrestore(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1892 struct gpii *gpii = gchan->gpii; in gpi_ch_init()
1893 const int ev_factor = gpii->gpi_dev->ev_factor; in gpi_ch_init()
1897 gchan->pm_state = CONFIG_STATE; in gpi_ch_init()
1901 if (gpii->gchan[i].pm_state != CONFIG_STATE) in gpi_ch_init()
1905 if (gpii->gchan[0].protocol != gpii->gchan[1].protocol) { in gpi_ch_init()
1906 dev_err(gpii->gpi_dev->dev, "protocol did not match protocol %u != %u\n", in gpi_ch_init()
1907 gpii->gchan[0].protocol, gpii->gchan[1].protocol); in gpi_ch_init()
1908 ret = -EINVAL; in gpi_ch_init()
1914 ret = gpi_alloc_ring(&gpii->ev_ring, elements, in gpi_ch_init()
1920 write_lock_irq(&gpii->pm_lock); in gpi_ch_init()
1921 gpii->pm_state = PREPARE_HARDWARE; in gpi_ch_init()
1922 write_unlock_irq(&gpii->pm_lock); in gpi_ch_init()
1925 dev_err(gpii->gpi_dev->dev, "error config. interrupts, ret:%d\n", ret); in gpi_ch_init()
1932 dev_err(gpii->gpi_dev->dev, "error alloc_ev_chan:%d\n", ret); in gpi_ch_init()
1938 ret = gpi_alloc_chan(&gpii->gchan[i], true); in gpi_ch_init()
1940 dev_err(gpii->gpi_dev->dev, "Error allocating chan:%d\n", ret); in gpi_ch_init()
1947 ret = gpi_start_chan(&gpii->gchan[i]); in gpi_ch_init()
1949 dev_err(gpii->gpi_dev->dev, "Error start chan:%d\n", ret); in gpi_ch_init()
1956 for (i = i - 1; i >= 0; i--) { in gpi_ch_init()
1957 gpi_stop_chan(&gpii->gchan[i]); in gpi_ch_init()
1962 for (i = i - 1; i >= 0; i--) in gpi_ch_init()
1967 gpi_free_ring(&gpii->ev_ring, gpii); in gpi_ch_init()
1976 struct gpii *gpii = gchan->gpii; in gpi_free_chan_resources()
1980 mutex_lock(&gpii->ctrl_lock); in gpi_free_chan_resources()
1982 cur_state = gchan->pm_state; in gpi_free_chan_resources()
1985 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
1986 gchan->pm_state = PREPARE_TERMINATE; in gpi_free_chan_resources()
1987 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
1995 dev_err(gpii->gpi_dev->dev, "error resetting channel:%d\n", ret); in gpi_free_chan_resources()
2001 gpi_free_ring(&gchan->ch_ring, gpii); in gpi_free_chan_resources()
2002 vchan_free_chan_resources(&gchan->vc); in gpi_free_chan_resources()
2003 kfree(gchan->config); in gpi_free_chan_resources()
2005 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2006 gchan->pm_state = DISABLE_STATE; in gpi_free_chan_resources()
2007 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2011 if (gpii->gchan[i].ch_ring.configured) in gpi_free_chan_resources()
2015 cur_state = gpii->pm_state; in gpi_free_chan_resources()
2016 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2017 gpii->pm_state = PREPARE_TERMINATE; in gpi_free_chan_resources()
2018 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2021 tasklet_kill(&gpii->ev_task); in gpi_free_chan_resources()
2027 gpi_free_ring(&gpii->ev_ring, gpii); in gpi_free_chan_resources()
2034 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2035 gpii->pm_state = DISABLE_STATE; in gpi_free_chan_resources()
2036 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2039 mutex_unlock(&gpii->ctrl_lock); in gpi_free_chan_resources()
2046 struct gpii *gpii = gchan->gpii; in gpi_alloc_chan_resources()
2049 mutex_lock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2052 ret = gpi_alloc_ring(&gchan->ch_ring, CHAN_TRES, in gpi_alloc_chan_resources()
2059 mutex_unlock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2063 mutex_unlock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2074 for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) { in gpi_find_avail_gpii()
2075 if (!((1 << gpii) & gpi_dev->gpii_mask)) in gpi_find_avail_gpii()
2078 tx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_TX_CHAN]; in gpi_find_avail_gpii()
2079 rx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_RX_CHAN]; in gpi_find_avail_gpii()
2081 if (rx_chan->vc.chan.client_count && rx_chan->seid == seid) in gpi_find_avail_gpii()
2083 if (tx_chan->vc.chan.client_count && tx_chan->seid == seid) in gpi_find_avail_gpii()
2088 for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) { in gpi_find_avail_gpii()
2089 if (!((1 << gpii) & gpi_dev->gpii_mask)) in gpi_find_avail_gpii()
2092 tx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_TX_CHAN]; in gpi_find_avail_gpii()
2093 rx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_RX_CHAN]; in gpi_find_avail_gpii()
2096 if (tx_chan->vc.chan.client_count || in gpi_find_avail_gpii()
2097 rx_chan->vc.chan.client_count) in gpi_find_avail_gpii()
2105 return -EIO; in gpi_find_avail_gpii()
2112 struct gpi_dev *gpi_dev = (struct gpi_dev *)of_dma->of_dma_data; in gpi_of_dma_xlate()
2117 if (args->args_count < 3) { in gpi_of_dma_xlate()
2118 dev_err(gpi_dev->dev, "gpii require minimum 2 args, client passed:%d args\n", in gpi_of_dma_xlate()
2119 args->args_count); in gpi_of_dma_xlate()
2123 chid = args->args[0]; in gpi_of_dma_xlate()
2125 dev_err(gpi_dev->dev, "gpii channel:%d not valid\n", chid); in gpi_of_dma_xlate()
2129 seid = args->args[1]; in gpi_of_dma_xlate()
2134 dev_err(gpi_dev->dev, "no available gpii instances\n"); in gpi_of_dma_xlate()
2138 gchan = &gpi_dev->gpiis[gpii].gchan[chid]; in gpi_of_dma_xlate()
2139 if (gchan->vc.chan.client_count) { in gpi_of_dma_xlate()
2140 dev_err(gpi_dev->dev, "gpii:%d chid:%d seid:%d already configured\n", in gpi_of_dma_xlate()
2141 gpii, chid, gchan->seid); in gpi_of_dma_xlate()
2145 gchan->seid = seid; in gpi_of_dma_xlate()
2146 gchan->protocol = args->args[2]; in gpi_of_dma_xlate()
2148 return dma_get_slave_channel(&gchan->vc.chan); in gpi_of_dma_xlate()
2158 gpi_dev = devm_kzalloc(&pdev->dev, sizeof(*gpi_dev), GFP_KERNEL); in gpi_probe()
2160 return -ENOMEM; in gpi_probe()
2162 gpi_dev->dev = &pdev->dev; in gpi_probe()
2163 gpi_dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &gpi_dev->res); in gpi_probe()
2164 if (IS_ERR(gpi_dev->regs)) in gpi_probe()
2165 return PTR_ERR(gpi_dev->regs); in gpi_probe()
2166 gpi_dev->ee_base = gpi_dev->regs; in gpi_probe()
2168 ret = of_property_read_u32(gpi_dev->dev->of_node, "dma-channels", in gpi_probe()
2169 &gpi_dev->max_gpii); in gpi_probe()
2171 dev_err(gpi_dev->dev, "missing 'max-no-gpii' DT node\n"); in gpi_probe()
2175 ret = of_property_read_u32(gpi_dev->dev->of_node, "dma-channel-mask", in gpi_probe()
2176 &gpi_dev->gpii_mask); in gpi_probe()
2178 dev_err(gpi_dev->dev, "missing 'gpii-mask' DT node\n"); in gpi_probe()
2182 ee_offset = (uintptr_t)device_get_match_data(gpi_dev->dev); in gpi_probe()
2183 gpi_dev->ee_base = gpi_dev->ee_base - ee_offset; in gpi_probe()
2185 gpi_dev->ev_factor = EV_FACTOR; in gpi_probe()
2187 ret = dma_set_mask(gpi_dev->dev, DMA_BIT_MASK(64)); in gpi_probe()
2189 dev_err(gpi_dev->dev, "Error setting dma_mask to 64, ret:%d\n", ret); in gpi_probe()
2193 gpi_dev->gpiis = devm_kzalloc(gpi_dev->dev, sizeof(*gpi_dev->gpiis) * in gpi_probe()
2194 gpi_dev->max_gpii, GFP_KERNEL); in gpi_probe()
2195 if (!gpi_dev->gpiis) in gpi_probe()
2196 return -ENOMEM; in gpi_probe()
2199 INIT_LIST_HEAD(&gpi_dev->dma_device.channels); in gpi_probe()
2200 for (i = 0; i < gpi_dev->max_gpii; i++) { in gpi_probe()
2201 struct gpii *gpii = &gpi_dev->gpiis[i]; in gpi_probe()
2204 if (!((1 << i) & gpi_dev->gpii_mask)) in gpi_probe()
2208 gpii->ev_cntxt_base_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0); in gpi_probe()
2209 gpii->ev_cntxt_db_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0); in gpi_probe()
2210 gpii->ev_ring_rp_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_4_RING_RP_LSB; in gpi_probe()
2211 gpii->ev_cmd_reg = gpi_dev->ee_base + GPII_n_EV_CH_CMD_OFFS(i); in gpi_probe()
2212 gpii->ieob_clr_reg = gpi_dev->ee_base + GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(i); in gpi_probe()
2218 gpii->irq = ret; in gpi_probe()
2222 struct gchan *gchan = &gpii->gchan[chan]; in gpi_probe()
2225 gchan->ch_cntxt_base_reg = gpi_dev->ee_base + in gpi_probe()
2227 gchan->ch_cntxt_db_reg = gpi_dev->ee_base + in gpi_probe()
2229 gchan->ch_cmd_reg = gpi_dev->ee_base + GPII_n_CH_CMD_OFFS(i); in gpi_probe()
2232 vchan_init(&gchan->vc, &gpi_dev->dma_device); in gpi_probe()
2233 gchan->vc.desc_free = gpi_desc_free; in gpi_probe()
2234 gchan->chid = chan; in gpi_probe()
2235 gchan->gpii = gpii; in gpi_probe()
2236 gchan->dir = GPII_CHAN_DIR[chan]; in gpi_probe()
2238 mutex_init(&gpii->ctrl_lock); in gpi_probe()
2239 rwlock_init(&gpii->pm_lock); in gpi_probe()
2240 tasklet_init(&gpii->ev_task, gpi_ev_tasklet, in gpi_probe()
2242 init_completion(&gpii->cmd_completion); in gpi_probe()
2243 gpii->gpii_id = i; in gpi_probe()
2244 gpii->regs = gpi_dev->ee_base; in gpi_probe()
2245 gpii->gpi_dev = gpi_dev; in gpi_probe()
2251 dma_cap_zero(gpi_dev->dma_device.cap_mask); in gpi_probe()
2252 dma_cap_set(DMA_SLAVE, gpi_dev->dma_device.cap_mask); in gpi_probe()
2255 gpi_dev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in gpi_probe()
2256 gpi_dev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in gpi_probe()
2257 gpi_dev->dma_device.src_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; in gpi_probe()
2258 gpi_dev->dma_device.dst_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; in gpi_probe()
2259 gpi_dev->dma_device.device_alloc_chan_resources = gpi_alloc_chan_resources; in gpi_probe()
2260 gpi_dev->dma_device.device_free_chan_resources = gpi_free_chan_resources; in gpi_probe()
2261 gpi_dev->dma_device.device_tx_status = dma_cookie_status; in gpi_probe()
2262 gpi_dev->dma_device.device_issue_pending = gpi_issue_pending; in gpi_probe()
2263 gpi_dev->dma_device.device_prep_slave_sg = gpi_prep_slave_sg; in gpi_probe()
2264 gpi_dev->dma_device.device_config = gpi_peripheral_config; in gpi_probe()
2265 gpi_dev->dma_device.device_terminate_all = gpi_terminate_all; in gpi_probe()
2266 gpi_dev->dma_device.dev = gpi_dev->dev; in gpi_probe()
2267 gpi_dev->dma_device.device_pause = gpi_pause; in gpi_probe()
2268 gpi_dev->dma_device.device_resume = gpi_resume; in gpi_probe()
2271 ret = dma_async_device_register(&gpi_dev->dma_device); in gpi_probe()
2273 dev_err(gpi_dev->dev, "async_device_register failed ret:%d", ret); in gpi_probe()
2277 ret = of_dma_controller_register(gpi_dev->dev->of_node, in gpi_probe()
2280 dev_err(gpi_dev->dev, "of_dma_controller_reg failed ret:%d", ret); in gpi_probe()
2288 { .compatible = "qcom,sdm845-gpi-dma", .data = (void *)0x0 },
2289 { .compatible = "qcom,sm6350-gpi-dma", .data = (void *)0x10000 },
2292 * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma
2295 { .compatible = "qcom,sc7280-gpi-dma", .data = (void *)0x10000 },
2296 { .compatible = "qcom,sm8150-gpi-dma", .data = (void *)0x0 },
2297 { .compatible = "qcom,sm8250-gpi-dma", .data = (void *)0x0 },
2298 { .compatible = "qcom,sm8350-gpi-dma", .data = (void *)0x10000 },
2299 { .compatible = "qcom,sm8450-gpi-dma", .data = (void *)0x10000 },
2318 MODULE_DESCRIPTION("QCOM GPI DMA engine driver");