Lines Matching refs:DMA_CCTRL
57 #define DMA_CCTRL 0x001C macro
528 reg = readl(d->base + DMA_CCTRL); in ldma_chan_cctrl_cfg()
542 writel(val, d->base + DMA_CCTRL); in ldma_chan_cctrl_cfg()
591 DMA_CCTRL); in ldma_chan_set_class()
605 ldma_update_bits(d, DMA_CCTRL_ON, DMA_CCTRL_ON, DMA_CCTRL); in ldma_chan_on()
622 ldma_update_bits(d, DMA_CCTRL_ON, 0, DMA_CCTRL); in ldma_chan_off()
625 ret = readl_poll_timeout_atomic(d->base + DMA_CCTRL, val, in ldma_chan_off()
650 FIELD_PREP(DMA_CDBA_MSB, hi), DMA_CCTRL); in ldma_chan_desc_hw_cfg()
707 ldma_update_bits(d, DMA_CCTRL_RST, DMA_CCTRL_RST, DMA_CCTRL); in ldma_chan_reset()
710 ret = readl_poll_timeout_atomic(d->base + DMA_CCTRL, val, in ldma_chan_reset()
800 ldma_update_bits(d, mask, val, DMA_CCTRL); in ldma_chan_rxwr_np_cfg()
815 ldma_update_bits(d, mask, val, DMA_CCTRL); in ldma_chan_abc_cfg()