243 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)  in imx_dmav1_readl()  function
283 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),  in imxdma_sg_next()
284 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),  in imxdma_sg_next()
285 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));  in imxdma_sg_next()
300 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &  in imxdma_enable_hw()
302 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |  in imxdma_enable_hw()
311 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));  in imxdma_enable_hw()
332 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |  in imxdma_disable_hw()
334 	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &  in imxdma_disable_hw()
361 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in imxdma_err_handler()
363 	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |  in imxdma_err_handler()
364 		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |  in imxdma_err_handler()
365 		   imx_dmav1_readl(imxdma, DMA_DSESR)  |  in imxdma_err_handler()
366 		   imx_dmav1_readl(imxdma, DMA_DBOSR);  in imxdma_err_handler()
378 		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {  in imxdma_err_handler()
382 		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {  in imxdma_err_handler()
386 		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {  in imxdma_err_handler()
390 		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {  in imxdma_err_handler()
432 			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));  in dma_irq_handle_channel()
478 	disr = imx_dmav1_readl(imxdma, DMA_DISR);  in dma_irq_handler()