Lines Matching refs:DMA_CCR
69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ macro
302 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | in imxdma_enable_hw()
303 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); in imxdma_enable_hw()
311 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); in imxdma_enable_hw()
313 DMA_CCR(channel)); in imxdma_enable_hw()
334 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & in imxdma_disable_hw()
335 ~CCR_CEN, DMA_CCR(channel)); in imxdma_disable_hw()
346 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); in imxdma_watchdog()
432 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); in dma_irq_handle_channel()
442 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
445 DMA_CCR(chno)); in dma_irq_handle_channel()
449 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
465 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); in dma_irq_handle_channel()
544 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
562 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
573 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()