31 #define RING_WRITE_SLOT		GENMASK(1, 0)
37 #define STATUS_DESC_DONE	BIT(0)
42 #define REG_TX_START		0x0000
43 #define REG_TX_STOP		0x0004
44 #define REG_RX_START		0x0008
45 #define REG_RX_STOP		0x000c
46 #define REG_IMPRINT		0x0090
47 #define REG_TX_SRAM_SIZE	0x0094
48 #define REG_RX_SRAM_SIZE	0x0098
50 #define REG_CHAN_CTL(ch)	(0x8000 + (ch) * 0x200)
51 #define REG_CHAN_CTL_RST_RINGS	BIT(0)
53 #define REG_DESC_RING(ch)	(0x8070 + (ch) * 0x200)
54 #define REG_REPORT_RING(ch)	(0x8074 + (ch) * 0x200)
56 #define REG_RESIDUE(ch)		(0x8064 + (ch) * 0x200)
58 #define REG_BUS_WIDTH(ch)	(0x8040 + (ch) * 0x200)
60 #define BUS_WIDTH_8BIT		0x00
61 #define BUS_WIDTH_16BIT		0x01
62 #define BUS_WIDTH_32BIT		0x02
63 #define BUS_WIDTH_FRAME_2_WORDS	0x10
64 #define BUS_WIDTH_FRAME_4_WORDS	0x20
66 #define REG_CHAN_SRAM_CARVEOUT(ch)	(0x8050 + (ch) * 0x200)
68 #define CHAN_SRAM_CARVEOUT_BASE		GENMASK(15, 0)
70 #define REG_CHAN_FIFOCTL(ch)	(0x8054 + (ch) * 0x200)
72 #define CHAN_FIFOCTL_THRESHOLD	GENMASK(15, 0)
74 #define REG_DESC_WRITE(ch)	(0x10000 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
75 #define REG_REPORT_READ(ch)	(0x10100 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
77 #define REG_TX_INTSTATE(idx)		(0x0030 + (idx) * 4)
78 #define REG_RX_INTSTATE(idx)		(0x0040 + (idx) * 4)
79 #define REG_GLOBAL_INTSTATE(idx)	(0x0050 + (idx) * 4)
80 #define REG_CHAN_INTSTATUS(ch, idx)	(0x8010 + (ch) * 0x200 + (idx) * 4)
81 #define REG_CHAN_INTMASK(ch, idx)	(0x8020 + (ch) * 0x200 + (idx) * 4)
153 	int i, ret = 0, nblocks;  in admac_alloc_sram_carveout()
163 	for (i = 0; i < nblocks; i++)  in admac_alloc_sram_carveout()
245 	return 0;  in admac_desc_free()
270 	adtx->submitted_pos = 0;  in admac_prep_dma_cyclic()
271 	adtx->reclaimed_pos = 0;  in admac_prep_dma_cyclic()
293 	dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n",  in admac_cyclic_write_one_desc()
314 	for (i = 0; i < 4; i++) {  in admac_cyclic_write_desc()
329 		WARN_ON((ringval & (RING_FULL | RING_EMPTY)) == 0);  in admac_ring_noccupied_slots()
334 			return 0;  in admac_ring_noccupied_slots()
393 		residue = 0;  in admac_tx_status()
454 	writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));  in admac_reset_rings()
463 	writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));  in admac_start_current_tx()
483 		adchan->nperiod_acks = 0;  in admac_issue_pending()
495 	return 0;  in admac_pause()
504 	return 0;  in admac_resume()
528 	return 0;  in admac_terminate_all()
559 	if (ret < 0)  in admac_alloc_chan_resources()
564 	return 0;  in admac_alloc_chan_resources()
586 	index = dma_spec->args[0];  in admac_dma_of_xlate()
600 	for (count = 0; count < 4; count++) {  in admac_drain_reports()
611 		dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n",  in admac_drain_reports()
637 			     STATUS_ERR, 0);  in admac_handle_status_err()
690 	for (i = 0; i < ad->nchannels; i += 2) {  in admac_interrupt()
705 		writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));  in admac_interrupt()
722 	adchan->nperiod_acks = 0;  in admac_chan_tasklet()
729 	tx_result.residue = 0;  in admac_chan_tasklet()
742 	int wordsize = 0;  in admac_device_config()
743 	u32 bus_width = 0;  in admac_device_config()
770 	case 0 ... 1:  in admac_device_config()
791 	writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize)  in admac_device_config()
792 		       | FIELD_PREP(CHAN_FIFOCTL_THRESHOLD, 0x18 * wordsize),  in admac_device_config()
795 	return 0;  in admac_device_config()
825 	for (i = 0; i < IRQ_NOUTPUTS; i++) {  in admac_probe()
827 		if (irq >= 0) {  in admac_probe()
833 	if (irq < 0)  in admac_probe()
837 	ad->base = devm_platform_ioremap_resource(pdev, 0);  in admac_probe()
873 	for (i = 0; i < nchannels; i++) {  in admac_probe()
892 	err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad);  in admac_probe()
919 	return 0;  in admac_probe()
937 	return 0;  in admac_remove()