153 	struct me_private_data *devpriv = dev->private;  in me_dio_insn_config()  local
168 		devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA;  in me_dio_insn_config()
170 		devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA;  in me_dio_insn_config()
172 		devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA;  in me_dio_insn_config()
174 		devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA;  in me_dio_insn_config()
176 	writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);  in me_dio_insn_config()
232 	struct me_private_data *devpriv = dev->private;  in me_ai_insn_read()  local
250 	devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);  in me_ai_insn_read()
251 	writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);  in me_ai_insn_read()
256 	devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);  in me_ai_insn_read()
257 	writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);  in me_ai_insn_read()
268 	devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG;  in me_ai_insn_read()
269 	writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);  in me_ai_insn_read()
288 	devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;  in me_ai_insn_read()
289 	writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);  in me_ai_insn_read()
299 	struct me_private_data *devpriv = dev->private;  in me_ao_insn_write()  local
306 	devpriv->ctrl2 |= ME_CTRL2_DAC_ENA;  in me_ao_insn_write()
307 	writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);  in me_ao_insn_write()
310 	devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC;  in me_ao_insn_write()
311 	writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);  in me_ao_insn_write()
314 	devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan);  in me_ao_insn_write()
316 		devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan);  in me_ao_insn_write()
318 		devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan);  in me_ao_insn_write()
319 	writew(devpriv->dac_ctrl, dev->mmio + ME_DAC_CTRL_REG);  in me_ao_insn_write()
342 	struct me_private_data *devpriv = dev->private;  in me2600_xilinx_download()  local
348 	writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);  in me2600_xilinx_download()
388 	value = readl(devpriv->plx_regbase + PLX9052_INTCSR);  in me2600_xilinx_download()
391 		writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);  in me2600_xilinx_download()
403 	       devpriv->plx_regbase + PLX9052_INTCSR);  in me2600_xilinx_download()
410 	struct me_private_data *devpriv = dev->private;  in me_reset()  local
419 	devpriv->dac_ctrl = 0;  in me_reset()
420 	devpriv->ctrl1 = 0;  in me_reset()
421 	devpriv->ctrl2 = 0;  in me_reset()
431 	struct me_private_data *devpriv;  in me_auto_attach()  local
442 	devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));  in me_auto_attach()
443 	if (!devpriv)  in me_auto_attach()
450 	devpriv->plx_regbase = pci_ioremap_bar(pcidev, 0);  in me_auto_attach()
451 	if (!devpriv->plx_regbase)  in me_auto_attach()
513 	struct me_private_data *devpriv = dev->private;  in me_detach()  local
515 	if (devpriv) {  in me_detach()
518 		if (devpriv->plx_regbase)  in me_detach()
519 			iounmap(devpriv->plx_regbase);  in me_detach()