Lines Matching +full:binary +full:- +full:coded
1 // SPDX-License-Identifier: GPL-2.0+
5 * ME-2000i, ME-2600i, ME-3000vm1
13 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
35 * PCI BAR2 Memory map (dev->mmio)
76 #define ME_TIMER_DATA_REG(x) (0x0a + ((x) * 2)) /* - | W */
83 #define ME_DAC_CTRL_BIPOLAR(x) BIT(7 - ((x) & 0x3))
84 #define ME_DAC_CTRL_GAIN(x) BIT(11 - ((x) & 0x3))
87 #define ME_AO_DATA_REG(x) (0x14 + ((x) * 2)) /* - | W */
88 #define ME_COUNTER_ENDDATA_REG(x) (0x1c + ((x) * 2)) /* - | W */
89 #define ME_COUNTER_STARTDATA_REG(x) (0x20 + ((x) * 2)) /* - | W */
90 #define ME_COUNTER_VALUE_REG(x) (0x20 + ((x) * 2)) /* R | - */
126 .name = "me-2600i",
131 .name = "me-2000i",
153 struct me_private_data *devpriv = dev->private; in me_dio_insn_config()
154 unsigned int chan = CR_CHAN(insn->chanspec); in me_dio_insn_config()
167 if (s->io_bits & 0x0000ffff) in me_dio_insn_config()
168 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
170 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
171 if (s->io_bits & 0xffff0000) in me_dio_insn_config()
172 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
174 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
178 return insn->n; in me_dio_insn_config()
186 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG; in me_dio_insn_bits()
187 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG; in me_dio_insn_bits()
194 writew((s->state & 0xffff), mmio_porta); in me_dio_insn_bits()
196 writew(((s->state >> 16) & 0xffff), mmio_portb); in me_dio_insn_bits()
199 if (s->io_bits & 0x0000ffff) in me_dio_insn_bits()
200 val = s->state & 0xffff; in me_dio_insn_bits()
204 if (s->io_bits & 0xffff0000) in me_dio_insn_bits()
205 val |= (s->state & 0xffff0000); in me_dio_insn_bits()
211 return insn->n; in me_dio_insn_bits()
221 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
224 return -EBUSY; in me_ai_eoc()
232 struct me_private_data *devpriv = dev->private; in me_ai_insn_read()
233 unsigned int chan = CR_CHAN(insn->chanspec); in me_ai_insn_read()
234 unsigned int range = CR_RANGE(insn->chanspec); in me_ai_insn_read()
235 unsigned int aref = CR_AREF(insn->chanspec); in me_ai_insn_read()
246 return -EINVAL; in me_ai_insn_read()
250 devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); in me_ai_insn_read()
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_ai_insn_read()
256 devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); in me_ai_insn_read()
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
265 writew(val, dev->mmio + ME_AI_FIFO_REG); in me_ai_insn_read()
268 devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG; in me_ai_insn_read()
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
271 for (i = 0; i < insn->n; i++) { in me_ai_insn_read()
273 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
281 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata; in me_ai_insn_read()
283 /* munge 2's complement value to offset binary */ in me_ai_insn_read()
288 devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK; in me_ai_insn_read()
289 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
291 return ret ? ret : insn->n; in me_ai_insn_read()
299 struct me_private_data *devpriv = dev->private; in me_ao_insn_write()
300 unsigned int chan = CR_CHAN(insn->chanspec); in me_ao_insn_write()
301 unsigned int range = CR_RANGE(insn->chanspec); in me_ao_insn_write()
302 unsigned int val = s->readback[chan]; in me_ao_insn_write()
306 devpriv->ctrl2 |= ME_CTRL2_DAC_ENA; in me_ao_insn_write()
307 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
310 devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC; in me_ao_insn_write()
311 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
313 /* Set dac-control register */ in me_ao_insn_write()
314 devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan); in me_ao_insn_write()
316 devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan); in me_ao_insn_write()
318 devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan); in me_ao_insn_write()
319 writew(devpriv->dac_ctrl, dev->mmio + ME_DAC_CTRL_REG); in me_ao_insn_write()
321 /* Update dac-control register */ in me_ao_insn_write()
322 readw(dev->mmio + ME_DAC_CTRL_REG); in me_ao_insn_write()
325 for (i = 0; i < insn->n; i++) { in me_ao_insn_write()
328 writew(val, dev->mmio + ME_AO_DATA_REG(chan)); in me_ao_insn_write()
330 s->readback[chan] = val; in me_ao_insn_write()
333 readw(dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
335 return insn->n; in me_ao_insn_write()
342 struct me_private_data *devpriv = dev->private; in me2600_xilinx_download()
348 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR); in me2600_xilinx_download()
351 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET); in me2600_xilinx_download()
357 writeb(0x00, dev->mmio + 0x0); in me2600_xilinx_download()
362 * Build longs from the byte-wise coded header in me2600_xilinx_download()
363 * Byte 1-3: length of the array in me2600_xilinx_download()
364 * Byte 4-7: version in me2600_xilinx_download()
365 * Byte 8-11: date in me2600_xilinx_download()
366 * Byte 12-15: reserved in me2600_xilinx_download()
369 return -EINVAL; in me2600_xilinx_download()
381 writeb((data[16 + i] & 0xff), dev->mmio + 0x0); in me2600_xilinx_download()
385 writeb(0x00, dev->mmio + 0x0); in me2600_xilinx_download()
387 /* Test if there was an error during download -> INTB was thrown */ in me2600_xilinx_download()
388 value = readl(devpriv->plx_regbase + PLX9052_INTCSR); in me2600_xilinx_download()
391 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR); in me2600_xilinx_download()
392 dev_err(dev->class_dev, "Xilinx download failed\n"); in me2600_xilinx_download()
393 return -EIO; in me2600_xilinx_download()
399 /* Enable PLX-Interrupts */ in me2600_xilinx_download()
403 devpriv->plx_regbase + PLX9052_INTCSR); in me2600_xilinx_download()
410 struct me_private_data *devpriv = dev->private; in me_reset()
413 writew(0x00, dev->mmio + ME_CTRL1_REG); in me_reset()
414 writew(0x00, dev->mmio + ME_CTRL2_REG); in me_reset()
415 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_reset()
416 writew(0x00, dev->mmio + ME_DAC_CTRL_REG); in me_reset()
419 devpriv->dac_ctrl = 0; in me_reset()
420 devpriv->ctrl1 = 0; in me_reset()
421 devpriv->ctrl2 = 0; in me_reset()
438 return -ENODEV; in me_auto_attach()
439 dev->board_ptr = board; in me_auto_attach()
440 dev->board_name = board->name; in me_auto_attach()
444 return -ENOMEM; in me_auto_attach()
450 devpriv->plx_regbase = pci_ioremap_bar(pcidev, 0); in me_auto_attach()
451 if (!devpriv->plx_regbase) in me_auto_attach()
452 return -ENOMEM; in me_auto_attach()
454 dev->mmio = pci_ioremap_bar(pcidev, 2); in me_auto_attach()
455 if (!dev->mmio) in me_auto_attach()
456 return -ENOMEM; in me_auto_attach()
459 if (board->needs_firmware) { in me_auto_attach()
460 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev, in me_auto_attach()
472 s = &dev->subdevices[0]; in me_auto_attach()
473 s->type = COMEDI_SUBD_AI; in me_auto_attach()
474 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_DIFF; in me_auto_attach()
475 s->n_chan = 16; in me_auto_attach()
476 s->maxdata = 0x0fff; in me_auto_attach()
477 s->len_chanlist = 16; in me_auto_attach()
478 s->range_table = &me_ai_range; in me_auto_attach()
479 s->insn_read = me_ai_insn_read; in me_auto_attach()
481 s = &dev->subdevices[1]; in me_auto_attach()
482 if (board->has_ao) { in me_auto_attach()
483 s->type = COMEDI_SUBD_AO; in me_auto_attach()
484 s->subdev_flags = SDF_WRITABLE | SDF_COMMON; in me_auto_attach()
485 s->n_chan = 4; in me_auto_attach()
486 s->maxdata = 0x0fff; in me_auto_attach()
487 s->len_chanlist = 4; in me_auto_attach()
488 s->range_table = &me_ao_range; in me_auto_attach()
489 s->insn_write = me_ao_insn_write; in me_auto_attach()
495 s->type = COMEDI_SUBD_UNUSED; in me_auto_attach()
498 s = &dev->subdevices[2]; in me_auto_attach()
499 s->type = COMEDI_SUBD_DIO; in me_auto_attach()
500 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in me_auto_attach()
501 s->n_chan = 32; in me_auto_attach()
502 s->maxdata = 1; in me_auto_attach()
503 s->len_chanlist = 32; in me_auto_attach()
504 s->range_table = &range_digital; in me_auto_attach()
505 s->insn_bits = me_dio_insn_bits; in me_auto_attach()
506 s->insn_config = me_dio_insn_config; in me_auto_attach()
513 struct me_private_data *devpriv = dev->private; in me_detach()
516 if (dev->mmio) in me_detach()
518 if (devpriv->plx_regbase) in me_detach()
519 iounmap(devpriv->plx_regbase); in me_detach()
534 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data); in me_daq_pci_probe()
553 MODULE_DESCRIPTION("Comedi low-level driver");