1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
7  * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16  * DOC: basic adjustable divider clock that cannot gate
18  * Traits of this clock:
19  * prepare - clk_prepare only ensures that parents are prepared
20  * enable - clk_enable only ensures that parents are enabled
21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
22  * parent - fixed parent.  No clk_set_parent support
32  * struct zynqmp_clk_divider - adjustable divider clock
33  * @hw:		handle between common and hardware-specific interfaces
36  * @clk_id:	Id of clock
65 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
73  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
74  * @hw:			handle between common and hardware-specific interfaces
75  * @parent_rate:	rate of parent clock
84 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
85 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
86 	u32 div, value;  in zynqmp_clk_divider_recalc_rate()  local
89 	ret = zynqmp_pm_clock_getdivider(clk_id, &div);  in zynqmp_clk_divider_recalc_rate()
96 		value = div & 0xFFFF;  in zynqmp_clk_divider_recalc_rate()
98 		value = div >> 16;  in zynqmp_clk_divider_recalc_rate()
100 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
104 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
139 	for (div1 = 1; div1 <= pdivider->max_div;) {  in zynqmp_get_divider2_val()
140 		for (div2 = 1; div2 <= divider->max_div;) {  in zynqmp_get_divider2_val()
141 			long new_error = ((div1_prate / div1) / div2) - rate;  in zynqmp_get_divider2_val()
147 			if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_get_divider2_val()
152 		if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_get_divider2_val()
160  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
161  * @hw:			handle between common and hardware-specific interfaces
162  * @rate:		rate of clock to be set
163  * @prate:		rate of parent clock
173 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_round_rate()
174 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_round_rate()
179 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_round_rate()
190 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_round_rate()
196 	bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);  in zynqmp_clk_divider_round_rate()
208 	if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)  in zynqmp_clk_divider_round_rate()
211 	bestdiv = min_t(u32, bestdiv, divider->max_div);  in zynqmp_clk_divider_round_rate()
218  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
219  * @hw:			handle between common and hardware-specific interfaces
220  * @rate:		rate of clock to be set
221  * @parent_rate:	rate of parent clock
230 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
231 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
232 	u32 value, div;  in zynqmp_clk_divider_set_rate()  local
235 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
237 		div = value & 0xFFFF;  in zynqmp_clk_divider_set_rate()
238 		div |= 0xffff << 16;  in zynqmp_clk_divider_set_rate()
240 		div = 0xffff;  in zynqmp_clk_divider_set_rate()
241 		div |= value << 16;  in zynqmp_clk_divider_set_rate()
244 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
245 		div = __ffs(div);  in zynqmp_clk_divider_set_rate()
247 	ret = zynqmp_pm_clock_setdivider(clk_id, div);  in zynqmp_clk_divider_set_rate()
268  * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
269  * @clk_id:		Id of clock
272  * Return: Maximum divisor of a clock if query data is successful
319  * zynqmp_clk_register_divider() - Register a divider clock
320  * @name:		Name of this clock
321  * @clk_id:		Id of clock
322  * @parents:		Name of this clock's parents
324  * @nodes:		Clock topology node
326  * Return: clock hardware to registered clock divider
334 	struct zynqmp_clk_divider *div;  in zynqmp_clk_register_divider()  local
340 	div = kzalloc(sizeof(*div), GFP_KERNEL);  in zynqmp_clk_register_divider()
341 	if (!div)  in zynqmp_clk_register_divider()
342 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_divider()
345 	if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)  in zynqmp_clk_register_divider()
350 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_divider()
356 	div->is_frac = !!((nodes->flag & CLK_FRAC) |  in zynqmp_clk_register_divider()
357 			  (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));  in zynqmp_clk_register_divider()
358 	div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);  in zynqmp_clk_register_divider()
359 	div->hw.init = &init;  in zynqmp_clk_register_divider()
360 	div->clk_id = clk_id;  in zynqmp_clk_register_divider()
361 	div->div_type = nodes->type;  in zynqmp_clk_register_divider()
367 	div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);  in zynqmp_clk_register_divider()
369 	hw = &div->hw;  in zynqmp_clk_register_divider()
372 		kfree(div);  in zynqmp_clk_register_divider()