56 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
74 /* Extract divider instance from clock hardware instance */
110  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
113  * @base:	base address of register containing the divider
114  * @offset:	offset address of register containing the divider
115  * @shift:	shift to the divider bit field
116  * @width:	width of the divider bit field
117  * @flags:	clk_wzrd divider flags
118  * @table:	array of value/divider pairs, last entry should have div = 0
120  * @d:	value of the common divider
121  * @o:	value of the leaf divider
135 	spinlock_t *lock;  /* divider lock */
153 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate()  local
154 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate()
157 	val = readl(div_addr) >> divider->shift;  in clk_wzrd_recalc_rate()
158 	val &= div_mask(divider->width);  in clk_wzrd_recalc_rate()
160 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_wzrd_recalc_rate()
161 			divider->flags, divider->width);  in clk_wzrd_recalc_rate()
170 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig()  local
171 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig()
173 	if (divider->lock)  in clk_wzrd_dynamic_reconfig()
174 		spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
176 		__acquire(divider->lock);  in clk_wzrd_dynamic_reconfig()
188 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
196 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
198 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
201 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
205 	if (divider->lock)  in clk_wzrd_dynamic_reconfig()
206 		spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
208 		__release(divider->lock);  in clk_wzrd_dynamic_reconfig()
229 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors()  local
242 						divider->m = m;  in clk_wzrd_get_divisors()
243 						divider->d = d;  in clk_wzrd_get_divisors()
244 						divider->o = o;  in clk_wzrd_get_divisors()
257 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_nolock()  local
266 	vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d);  in clk_wzrd_dynamic_all_nolock()
278 	writel(reg, divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_dynamic_all_nolock()
280 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |  in clk_wzrd_dynamic_all_nolock()
281 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);  in clk_wzrd_dynamic_all_nolock()
282 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0));  in clk_wzrd_dynamic_all_nolock()
283 	writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_dynamic_all_nolock()
284 	writel(0, divider->base + WZRD_CLK_CFG_REG(3));  in clk_wzrd_dynamic_all_nolock()
286 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_all_nolock()
294 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_all_nolock()
297 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_all_nolock()
305 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all()  local
309 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all()
313 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all()
321 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all()  local
324 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0));  in clk_wzrd_recalc_rate_all()
327 	reg = readl(divider->base + WZRD_CLK_CFG_REG(2));  in clk_wzrd_recalc_rate_all()
332 	return divider_recalc_rate(hw, parent_rate * m, div, divider->table,  in clk_wzrd_recalc_rate_all()
333 			divider->flags, divider->width);  in clk_wzrd_recalc_rate_all()
339 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_round_rate_all()  local
348 	m = divider->m;  in clk_wzrd_round_rate_all()
349 	d = divider->d;  in clk_wzrd_round_rate_all()
350 	o = divider->o;  in clk_wzrd_round_rate_all()
353 	int_freq =  divider_recalc_rate(hw, *prate * m, div, divider->table,  in clk_wzrd_round_rate_all()
354 					divider->flags, divider->width);  in clk_wzrd_round_rate_all()
380 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_ratef()  local
381 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_ratef()
384 	div = val & div_mask(divider->width);  in clk_wzrd_recalc_ratef()
396 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig_f()  local
397 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig_f()
414 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
422 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
424 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
427 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
705 		dev_err(&pdev->dev, "unable to register divider clock\n");  in clk_wzrd_probe()
743 				"unable to register divider clock\n");  in clk_wzrd_probe()