163 	clk = of_clk_get(node, 0);  in _register_dpll()
227 	parent_name = of_clk_get_parent_name(node, 0);  in _register_dpll_x2()
252 		if (ret <= 0) {  in _register_dpll_x2()
254 		} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {  in _register_dpll_x2()
288 	u8 dpll_mode = 0;  in of_ti_dpll_setup()
318 	if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))  in of_ti_dpll_setup()
416 		.idlest_mask = 0x1,  in of_ti_omap3_dpll_setup()
417 		.enable_mask = 0x7,  in of_ti_omap3_dpll_setup()
418 		.autoidle_mask = 0x7,  in of_ti_omap3_dpll_setup()
419 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_dpll_setup()
420 		.div1_mask = 0x7f,  in of_ti_omap3_dpll_setup()
424 		.freqsel_mask = 0xf0,  in of_ti_omap3_dpll_setup()
441 		.idlest_mask = 0x1,  in of_ti_omap3_core_dpll_setup()
442 		.enable_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
443 		.autoidle_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
444 		.mult_mask = 0x7ff << 16,  in of_ti_omap3_core_dpll_setup()
445 		.div1_mask = 0x7f << 8,  in of_ti_omap3_core_dpll_setup()
449 		.freqsel_mask = 0xf0,  in of_ti_omap3_core_dpll_setup()
460 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_dpll_setup()
461 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_dpll_setup()
462 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_dpll_setup()
463 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_per_dpll_setup()
464 		.div1_mask = 0x7f,  in of_ti_omap3_per_dpll_setup()
468 		.freqsel_mask = 0xf00000,  in of_ti_omap3_per_dpll_setup()
480 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_jtype_dpll_setup()
481 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_jtype_dpll_setup()
482 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_jtype_dpll_setup()
483 		.mult_mask = 0xfff << 8,  in of_ti_omap3_per_jtype_dpll_setup()
484 		.div1_mask = 0x7f,  in of_ti_omap3_per_jtype_dpll_setup()
488 		.sddiv_mask = 0xff << 24,  in of_ti_omap3_per_jtype_dpll_setup()
489 		.dco_mask = 0xe << 20,  in of_ti_omap3_per_jtype_dpll_setup()
503 		.idlest_mask = 0x1,  in of_ti_omap4_dpll_setup()
504 		.enable_mask = 0x7,  in of_ti_omap4_dpll_setup()
505 		.autoidle_mask = 0x7,  in of_ti_omap4_dpll_setup()
506 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_dpll_setup()
507 		.div1_mask = 0x7f,  in of_ti_omap4_dpll_setup()
522 		.idlest_mask = 0x1,  in of_ti_omap5_mpu_dpll_setup()
523 		.enable_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
524 		.autoidle_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
525 		.mult_mask = 0x7ff << 8,  in of_ti_omap5_mpu_dpll_setup()
526 		.div1_mask = 0x7f,  in of_ti_omap5_mpu_dpll_setup()
543 		.idlest_mask = 0x1,  in of_ti_omap4_core_dpll_setup()
544 		.enable_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
545 		.autoidle_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
546 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_core_dpll_setup()
547 		.div1_mask = 0x7f,  in of_ti_omap4_core_dpll_setup()
564 		.idlest_mask = 0x1,  in of_ti_omap4_m4xen_dpll_setup()
565 		.enable_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
566 		.autoidle_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
567 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_m4xen_dpll_setup()
568 		.div1_mask = 0x7f,  in of_ti_omap4_m4xen_dpll_setup()
572 		.m4xen_mask = 0x800,  in of_ti_omap4_m4xen_dpll_setup()
585 		.idlest_mask = 0x1,  in of_ti_omap4_jtype_dpll_setup()
586 		.enable_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
587 		.autoidle_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
588 		.mult_mask = 0xfff << 8,  in of_ti_omap4_jtype_dpll_setup()
589 		.div1_mask = 0xff,  in of_ti_omap4_jtype_dpll_setup()
593 		.sddiv_mask = 0xff << 24,  in of_ti_omap4_jtype_dpll_setup()
607 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_dpll_setup()
608 		.enable_mask = 0x7,  in of_ti_am3_no_gate_dpll_setup()
609 		.ssc_enable_mask = 0x1 << 12,  in of_ti_am3_no_gate_dpll_setup()
610 		.ssc_downspread_mask = 0x1 << 14,  in of_ti_am3_no_gate_dpll_setup()
611 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_dpll_setup()
612 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_dpll_setup()
613 		.ssc_deltam_int_mask = 0x3 << 18,  in of_ti_am3_no_gate_dpll_setup()
614 		.ssc_deltam_frac_mask = 0x3ffff,  in of_ti_am3_no_gate_dpll_setup()
615 		.ssc_modfreq_mant_mask = 0x7f,  in of_ti_am3_no_gate_dpll_setup()
616 		.ssc_modfreq_exp_mask = 0x7 << 8,  in of_ti_am3_no_gate_dpll_setup()
632 		.idlest_mask = 0x1,  in of_ti_am3_jtype_dpll_setup()
633 		.enable_mask = 0x7,  in of_ti_am3_jtype_dpll_setup()
634 		.mult_mask = 0x7ff << 8,  in of_ti_am3_jtype_dpll_setup()
635 		.div1_mask = 0x7f,  in of_ti_am3_jtype_dpll_setup()
652 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_jtype_dpll_setup()
653 		.enable_mask = 0x7,  in of_ti_am3_no_gate_jtype_dpll_setup()
654 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_jtype_dpll_setup()
655 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_jtype_dpll_setup()
673 		.idlest_mask = 0x1,  in of_ti_am3_dpll_setup()
674 		.enable_mask = 0x7,  in of_ti_am3_dpll_setup()
675 		.ssc_enable_mask = 0x1 << 12,  in of_ti_am3_dpll_setup()
676 		.ssc_downspread_mask = 0x1 << 14,  in of_ti_am3_dpll_setup()
677 		.mult_mask = 0x7ff << 8,  in of_ti_am3_dpll_setup()
678 		.div1_mask = 0x7f,  in of_ti_am3_dpll_setup()
679 		.ssc_deltam_int_mask = 0x3 << 18,  in of_ti_am3_dpll_setup()
680 		.ssc_deltam_frac_mask = 0x3ffff,  in of_ti_am3_dpll_setup()
681 		.ssc_modfreq_mant_mask = 0x7f,  in of_ti_am3_dpll_setup()
682 		.ssc_modfreq_exp_mask = 0x7 << 8,  in of_ti_am3_dpll_setup()
697 		.idlest_mask = 0x1,  in of_ti_am3_core_dpll_setup()
698 		.enable_mask = 0x7,  in of_ti_am3_core_dpll_setup()
699 		.mult_mask = 0x7ff << 8,  in of_ti_am3_core_dpll_setup()
700 		.div1_mask = 0x7f,  in of_ti_am3_core_dpll_setup()
716 		.enable_mask = 0x3,  in of_ti_omap2_core_dpll_setup()
717 		.mult_mask = 0x3ff << 12,  in of_ti_omap2_core_dpll_setup()
718 		.div1_mask = 0xf << 8,  in of_ti_omap2_core_dpll_setup()