Lines Matching +full:clock +full:- +full:output +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
177 const char *name; in ti_adpll_clk_get_name() local
181 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
182 "clock-output-names", in ti_adpll_clk_get_name()
184 &name); in ti_adpll_clk_get_name()
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
189 d->pa, postfix); in ti_adpll_clk_get_name()
192 return name; in ti_adpll_clk_get_name()
197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
198 int index, int output_index, const char *name, in ti_adpll_setup_clock() argument
205 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
206 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
209 postfix = strrchr(name, '.'); in ti_adpll_setup_clock()
212 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
213 name); in ti_adpll_setup_clock()
214 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1); in ti_adpll_setup_clock()
215 cl = clkdev_create(clock, con_id, NULL); in ti_adpll_setup_clock()
217 return -ENOMEM; in ti_adpll_setup_clock()
218 d->clocks[index].cl = cl; in ti_adpll_setup_clock()
220 dev_warn(d->dev, "no con_id for clock %s\n", name); in ti_adpll_setup_clock()
226 d->outputs.clks[output_index] = clock; in ti_adpll_setup_clock()
227 d->outputs.clk_num++; in ti_adpll_setup_clock()
234 int output_index, char *name, in ti_adpll_init_divider() argument
242 struct clk *clock; in ti_adpll_init_divider() local
244 child_name = ti_adpll_clk_get_name(d, output_index, name); in ti_adpll_init_divider()
246 return -EINVAL; in ti_adpll_init_divider()
249 clock = clk_register_divider(d->dev, child_name, parent_name, 0, in ti_adpll_init_divider()
251 &d->lock); in ti_adpll_init_divider()
252 if (IS_ERR(clock)) { in ti_adpll_init_divider()
253 dev_err(d->dev, "failed to register divider %s: %li\n", in ti_adpll_init_divider()
254 name, PTR_ERR(clock)); in ti_adpll_init_divider()
255 return PTR_ERR(clock); in ti_adpll_init_divider()
258 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_divider()
264 char *name, struct clk *clk0, in ti_adpll_init_mux() argument
271 struct clk *clock; in ti_adpll_init_mux() local
273 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_mux()
275 return -ENOMEM; in ti_adpll_init_mux()
278 clock = clk_register_mux(d->dev, child_name, parents, 2, 0, in ti_adpll_init_mux()
279 reg, shift, 1, 0, &d->lock); in ti_adpll_init_mux()
280 if (IS_ERR(clock)) { in ti_adpll_init_mux()
281 dev_err(d->dev, "failed to register mux %s: %li\n", in ti_adpll_init_mux()
282 name, PTR_ERR(clock)); in ti_adpll_init_mux()
283 return PTR_ERR(clock); in ti_adpll_init_mux()
286 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_mux()
292 int output_index, char *name, in ti_adpll_init_gate() argument
300 struct clk *clock; in ti_adpll_init_gate() local
302 child_name = ti_adpll_clk_get_name(d, output_index, name); in ti_adpll_init_gate()
304 return -EINVAL; in ti_adpll_init_gate()
307 clock = clk_register_gate(d->dev, child_name, parent_name, 0, in ti_adpll_init_gate()
309 &d->lock); in ti_adpll_init_gate()
310 if (IS_ERR(clock)) { in ti_adpll_init_gate()
311 dev_err(d->dev, "failed to register gate %s: %li\n", in ti_adpll_init_gate()
312 name, PTR_ERR(clock)); in ti_adpll_init_gate()
313 return PTR_ERR(clock); in ti_adpll_init_gate()
316 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_gate()
322 char *name, in ti_adpll_init_fixed_factor() argument
329 struct clk *clock; in ti_adpll_init_fixed_factor() local
331 child_name = ti_adpll_clk_get_name(d, -ENODEV, name); in ti_adpll_init_fixed_factor()
333 return -ENOMEM; in ti_adpll_init_fixed_factor()
336 clock = clk_register_fixed_factor(d->dev, child_name, parent_name, in ti_adpll_init_fixed_factor()
338 if (IS_ERR(clock)) in ti_adpll_init_fixed_factor()
339 return PTR_ERR(clock); in ti_adpll_init_fixed_factor()
341 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name, in ti_adpll_init_fixed_factor()
350 spin_lock_irqsave(&d->lock, flags); in ti_adpll_set_idle_bypass()
351 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
353 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_set_idle_bypass()
354 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_set_idle_bypass()
362 spin_lock_irqsave(&d->lock, flags); in ti_adpll_clear_idle_bypass()
363 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
365 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_clear_idle_bypass()
366 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_clear_idle_bypass()
373 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_clock_is_bypass()
380 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
385 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET); in ti_adpll_is_locked()
398 } while (retries--); in ti_adpll_wait_lock()
400 dev_err(d->dev, "pll failed to lock\n"); in ti_adpll_wait_lock()
401 return -ETIMEDOUT; in ti_adpll_wait_lock()
432 * Note that the DCO clock is never subject to bypass: if the PLL is off,
447 spin_lock_irqsave(&d->lock, flags); in ti_adpll_recalc_rate()
448 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET); in ti_adpll_recalc_rate()
450 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18; in ti_adpll_recalc_rate()
453 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18; in ti_adpll_recalc_rate()
454 spin_unlock_irqrestore(&d->lock, flags); in ti_adpll_recalc_rate()
458 if (d->c->is_type_s) { in ti_adpll_recalc_rate()
459 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET); in ti_adpll_recalc_rate()
485 struct clk *clock; in ti_adpll_init_dco() local
489 d->outputs.clks = devm_kcalloc(d->dev, in ti_adpll_init_dco()
493 if (!d->outputs.clks) in ti_adpll_init_dco()
494 return -ENOMEM; in ti_adpll_init_dco()
496 if (d->c->output_index < 0) in ti_adpll_init_dco()
501 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix); in ti_adpll_init_dco()
502 if (!init.name) in ti_adpll_init_dco()
503 return -EINVAL; in ti_adpll_init_dco()
505 init.parent_names = d->parent_names; in ti_adpll_init_dco()
506 init.num_parents = d->c->nr_max_inputs; in ti_adpll_init_dco()
509 d->dco.hw.init = &init; in ti_adpll_init_dco()
511 if (d->c->is_type_s) in ti_adpll_init_dco()
516 /* Internal input clock divider N2 */ in ti_adpll_init_dco()
517 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2", in ti_adpll_init_dco()
518 d->parent_clocks[TI_ADPLL_CLKINP], in ti_adpll_init_dco()
519 d->regs + ADPLL_MN2DIV_OFFSET, in ti_adpll_init_dco()
524 clock = devm_clk_register(d->dev, &d->dco.hw); in ti_adpll_init_dco()
525 if (IS_ERR(clock)) in ti_adpll_init_dco()
526 return PTR_ERR(clock); in ti_adpll_init_dco()
528 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index, in ti_adpll_init_dco()
529 init.name, NULL); in ti_adpll_init_dco()
535 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_enable()
545 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_disable()
554 struct clk_hw *gate_hw = &co->gate.hw; in ti_adpll_clkout_is_enabled()
565 struct ti_adpll_data *d = co->adpll; in ti_adpll_clkout_get_parent()
573 char *name, struct clk *clk0, in ti_adpll_init_clkout() argument
581 struct clk *clock; in ti_adpll_init_clkout() local
584 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL); in ti_adpll_init_clkout()
586 return -ENOMEM; in ti_adpll_init_clkout()
587 co->adpll = d; in ti_adpll_init_clkout()
589 err = of_property_read_string_index(d->np, in ti_adpll_init_clkout()
590 "clock-output-names", in ti_adpll_init_clkout()
596 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL); in ti_adpll_init_clkout()
598 return -ENOMEM; in ti_adpll_init_clkout()
600 init.name = child_name; in ti_adpll_init_clkout()
603 co->hw.init = &init; in ti_adpll_init_clkout()
609 ops->get_parent = ti_adpll_clkout_get_parent; in ti_adpll_init_clkout()
610 ops->determine_rate = __clk_mux_determine_rate; in ti_adpll_init_clkout()
612 co->gate.lock = &d->lock; in ti_adpll_init_clkout()
613 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; in ti_adpll_init_clkout()
614 co->gate.bit_idx = gate_bit; in ti_adpll_init_clkout()
615 ops->enable = ti_adpll_clkout_enable; in ti_adpll_init_clkout()
616 ops->disable = ti_adpll_clkout_disable; in ti_adpll_init_clkout()
617 ops->is_enabled = ti_adpll_clkout_is_enabled; in ti_adpll_init_clkout()
620 clock = devm_clk_register(d->dev, &co->hw); in ti_adpll_init_clkout()
621 if (IS_ERR(clock)) { in ti_adpll_init_clkout()
622 dev_err(d->dev, "failed to register output %s: %li\n", in ti_adpll_init_clkout()
623 name, PTR_ERR(clock)); in ti_adpll_init_clkout()
624 return PTR_ERR(clock); in ti_adpll_init_clkout()
627 return ti_adpll_setup_clock(d, clock, index, output_index, child_name, in ti_adpll_init_clkout()
635 if (!d->c->is_type_s) in ti_adpll_init_children_adpll_s()
640 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_s()
641 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_s()
642 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
648 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2", in ti_adpll_init_children_adpll_s()
649 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
650 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_s()
659 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
664 /* Output clkout with a mux and gate, sources from div2 or bypass */ in ti_adpll_init_children_adpll_s()
667 d->clocks[TI_ADPLL_DIV2].clk, in ti_adpll_init_children_adpll_s()
668 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
672 /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */ in ti_adpll_init_children_adpll_s()
674 "clkout2", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_s()
675 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_s()
680 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) { in ti_adpll_init_children_adpll_s()
682 d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_s()
683 d->parent_clocks[TI_ADPLL_CLKINPHIF], in ti_adpll_init_children_adpll_s()
684 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_s()
690 /* Output clkouthif with a divider M3, sources from hif */ in ti_adpll_init_children_adpll_s()
692 d->clocks[TI_ADPLL_HIF].clk, in ti_adpll_init_children_adpll_s()
693 d->regs + ADPLL_M3DIV_OFFSET, in ti_adpll_init_children_adpll_s()
700 /* Output clock dcoclkldo is the DCO */ in ti_adpll_init_children_adpll_s()
709 if (d->c->is_type_s) in ti_adpll_init_children_adpll_lj()
712 /* Output clkdcoldo, gated output of DCO */ in ti_adpll_init_children_adpll_lj()
714 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
715 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
721 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, in ti_adpll_init_children_adpll_lj()
722 "m2", d->clocks[TI_ADPLL_DCO].clk, in ti_adpll_init_children_adpll_lj()
723 d->regs + ADPLL_M2NDIV_OFFSET, in ti_adpll_init_children_adpll_lj()
730 /* Output clkoutldo, gated output of M2 */ in ti_adpll_init_children_adpll_lj()
732 "clkoutldo", d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
733 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
741 d->clocks[TI_ADPLL_N2].clk, in ti_adpll_init_children_adpll_lj()
742 d->parent_clocks[TI_ADPLL_CLKINPULOW], in ti_adpll_init_children_adpll_lj()
743 d->regs + ADPLL_CLKCTRL_OFFSET, in ti_adpll_init_children_adpll_lj()
748 /* Output clkout, sources M2 or bypass */ in ti_adpll_init_children_adpll_lj()
751 d->clocks[TI_ADPLL_M2].clk, in ti_adpll_init_children_adpll_lj()
752 d->clocks[TI_ADPLL_BYPASS].clk); in ti_adpll_init_children_adpll_lj()
763 for (i = TI_ADPLL_M3; i >= 0; i--) { in ti_adpll_free_resources()
764 struct ti_adpll_clock *ac = &d->clocks[i]; in ti_adpll_free_resources()
766 if (!ac || IS_ERR_OR_NULL(ac->clk)) in ti_adpll_free_resources()
768 if (ac->cl) in ti_adpll_free_resources()
769 clkdev_drop(ac->cl); in ti_adpll_free_resources()
770 if (ac->unregister) in ti_adpll_free_resources()
771 ac->unregister(ac->clk); in ti_adpll_free_resources()
789 if (d->c->is_type_s) { in ti_adpll_init_registers()
791 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET); in ti_adpll_init_registers()
794 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET; in ti_adpll_init_registers()
802 struct clk *clock; in ti_adpll_init_inputs() local
805 nr_inputs = of_clk_get_parent_count(d->np); in ti_adpll_init_inputs()
806 if (nr_inputs < d->c->nr_max_inputs) { in ti_adpll_init_inputs()
807 dev_err(d->dev, error, nr_inputs); in ti_adpll_init_inputs()
808 return -EINVAL; in ti_adpll_init_inputs()
810 of_clk_parent_fill(d->np, d->parent_names, nr_inputs); in ti_adpll_init_inputs()
812 clock = devm_clk_get(d->dev, d->parent_names[0]); in ti_adpll_init_inputs()
813 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
814 dev_err(d->dev, "could not get clkinp\n"); in ti_adpll_init_inputs()
815 return PTR_ERR(clock); in ti_adpll_init_inputs()
817 d->parent_clocks[TI_ADPLL_CLKINP] = clock; in ti_adpll_init_inputs()
819 clock = devm_clk_get(d->dev, d->parent_names[1]); in ti_adpll_init_inputs()
820 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
821 dev_err(d->dev, "could not get clkinpulow clock\n"); in ti_adpll_init_inputs()
822 return PTR_ERR(clock); in ti_adpll_init_inputs()
824 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock; in ti_adpll_init_inputs()
826 if (d->c->is_type_s) { in ti_adpll_init_inputs()
827 clock = devm_clk_get(d->dev, d->parent_names[2]); in ti_adpll_init_inputs()
828 if (IS_ERR(clock)) { in ti_adpll_init_inputs()
829 dev_err(d->dev, "could not get clkinphif clock\n"); in ti_adpll_init_inputs()
830 return PTR_ERR(clock); in ti_adpll_init_inputs()
832 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock; in ti_adpll_init_inputs()
847 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
848 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
849 .output_index = -EINVAL,
853 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
854 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
861 struct device_node *node = pdev->dev.of_node; in ti_adpll_probe()
862 struct device *dev = &pdev->dev; in ti_adpll_probe()
871 pdata = match->data; in ti_adpll_probe()
873 return -ENODEV; in ti_adpll_probe()
877 return -ENOMEM; in ti_adpll_probe()
878 d->dev = dev; in ti_adpll_probe()
879 d->np = node; in ti_adpll_probe()
880 d->c = pdata; in ti_adpll_probe()
881 dev_set_drvdata(d->dev, d); in ti_adpll_probe()
882 spin_lock_init(&d->lock); in ti_adpll_probe()
884 d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in ti_adpll_probe()
885 if (IS_ERR(d->iobase)) in ti_adpll_probe()
886 return PTR_ERR(d->iobase); in ti_adpll_probe()
887 d->pa = res->start; in ti_adpll_probe()
897 d->clocks = devm_kcalloc(d->dev, in ti_adpll_probe()
901 if (!d->clocks) in ti_adpll_probe()
902 return -ENOMEM; in ti_adpll_probe()
917 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs); in ti_adpll_probe()
932 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev); in ti_adpll_remove()
939 .name = "ti-adpll",
958 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
959 MODULE_ALIAS("platform:dm814-adpll-clock");