Lines Matching refs:PLLU_BASE
74 #define PLLU_BASE 0xc0 macro
2302 .base_reg = PLLU_BASE,
2916 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2921 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2924 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2932 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); in tegra210_enable_pllu()
2948 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2958 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2960 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2980 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2982 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
3273 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3302 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3309 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3316 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()